[PATCH V2] drm/i915/mtl: Update workaround 14018575942

reported from media team. V2(Matt): - Use correct WA number Fixes: 668f37e1ee11 ("drm/i915/mtl: Update workaround 14018778641") Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/intel_wor

[PATCH] drm/i915/mtl: Update workaround 14018778641

reported from media team. Fixes: 668f37e1ee11 ("drm/i915/mtl: Update workaround 14018778641") Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/d

[PATCH] Revert "drm/i915/mtl: Update workaround 14018778641"

Applying WA 14018778641 only on Compute engine has impact on Chrome related apps. Reverting this patch and applying WA to all engines is helping with performance on Chrome related apps. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3

[V2] drm/i915: Add workaround 14019877138

WA 14019877138 needed for Graphics 12.70/71 both V2(Jani): - Use drm/i915 Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt

[PATCH] drm/xe: Add workaround 14019877138

WA 14019877138 needed for Graphics 12.70/71 both Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3eacbc50caf8

[Intel-gfx] [PATCH] drm/i915/mtl: Update workaround 14016712196

Now this workaround is permanent workaround on MTL and DG2, earlier we used to apply on MTL A0 step only. VLK-45480 Fixes: d922b80b1010 ("drm/i915/gt: Add workaround 14016712196") Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++ 1 file

[Intel-gfx] [PATCH] drm/i915/mtl: Update workaround 14018778641

WA 14018778641 needs an update after recent performance data on MTL, aligning driver here with HW WA update. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers

[Intel-gfx] [PATCH V5] drm/i915/gt: Add workaround 14016712196

in API - Andi V2: - Fix kernel test robot warnings Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/ Reviewed-by: Andi Shyti Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 1 file changed, 38 insertions

[Intel-gfx] [PATCH V4] drm/i915/gt: Add workaround 14016712196

robot warnings Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/ Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 40 1 file changed, 40 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b

[Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196

Wa_14016712196 implementation for mtl Bspec: 72197 V3: - Wrap dummy pipe control stuff in API - Andi V2: - Fix kernel test robot warnings Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/ Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt

[Intel-gfx] [PATCH V2] drm/i915/gem: Use large rings for compute contexts

From: Chris Wilson Allow compute contexts to submit the maximal amount of work without blocking userspace. The original size for user LRC ring's (SZ_16K) was chosen to minimise memory consumption, without being so small as to frequently stall in the middle of workloads. With the main consumers

[Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196

Wa_14016712196 implementation for mtl Bspec: 72197 V2: - Fix kernel test robot warnings Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/ Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41

[Intel-gfx] [PATCH] drm/i915/gem: Use large rings for compute contexts

From: Chris Wilson Allow compute contexts to submit the maximal amount of work without blocking userspace. The original size for user LRC ring's (SZ_16K) was chosen to minimise memory consumption, without being so small as to frequently stall in the middle of workloads. With the main consumers

[Intel-gfx] [PATCH] drm/i915/gt: Add workaround 14016712196

Wa_14016712196 implementation for mtl Bspec: 72197 Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index

[Intel-gfx] [PATCH 0/2] drm/i915: Use gt_err inplace of pr_err

When we use gt_err we get GT info when that failure hits which helps in debugging. Cc: Andi Shyti Signed-off-by: Tejas Upadhyay Tejas Upadhyay (2): drm/i915/gt: Use gt_err for GT info drm/i915/selftests: Use gt_err for GT info drivers/gpu/drm/i915/gt/selftest_engine_pm.c| 3

[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Use gt_err for GT info

It will be more informative regarding GT if we use gt_err instead. Cc: Andi Shyti Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers

[Intel-gfx] [PATCH 1/2] drm/i915/gt: Use gt_err for GT info

It will be more informative regarding GT if we use gt_err instead. Cc: Andi Shyti Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm

[Intel-gfx] [PATCH] drm/i915/selftest: Record GT error for gt failure

igt_live_test has pr_err dumped in case of some GT failures. It will be more informative regarding GT if we use gt_err instead. Cc: Andi Shyti Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/selftests/igt_live_test.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH V2] drm/i915/mtl: Add workaround 14018778641

WA 18018781329 is applicable now across all MTL steppings. V2: - Remove IS_MTL check, code already running for MTL - Matt Cc: Matt Roper Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++--- 1 file changed, 14 insertions(+), 16 deletions

[Intel-gfx] [PATCH] drm/i915/mtl: Add workaround 14018778641

WA 18018781329 is applicable now across all MTL steppings. Cc: Matt Roper Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b

[Intel-gfx] [PATCH 3/3] drm/i915/selftests: Consider multi-gt instead of to_gt()

In order to enable complete multi-GT, loop through all the GTs, rather than relying on the to_gt(), which only provides a reference to the primary GT. Problem appear when it runs on platform like MTL where different set of engines are possible on different GTs. Signed-off-by: Tejas Upadhyay

[Intel-gfx] [PATCH 2/3] drm/i915/gem: Consider multi-gt instead of to_gt()

. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index a81fa6a20f5a

[Intel-gfx] [PATCH 1/3] drm/i915/gt: Consider multi-gt instead of to_gt()

: Andi Shyti Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index cd4f1b126f75..dcedff41a825 100644

[Intel-gfx] [PATCH 0/3] Consider multi-gt instead of to_gt()

on platform like MTL where different set of engines are possible on different GTs. Cc: Andi Shyti Signed-off-by: Tejas Upadhyay Tejas Upadhyay (3): drm/i915/gt: Consider multi-gt instead of to_gt() drm/i915/gem: Consider multi-gt instead of to_gt() drm/i915/selftests: Consider multi-gt

[Intel-gfx] [PATCH] drm/i915/gt: Consider multi-gt at all places

In order to make igt_live_test work in proper way, we need to consider multi-gt in all tests where igt_live_test is used as well as at other random places where multi-gt should be considered. Cc: Andi Shyti Signed-off-by: Tejas Upadhyay --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 13

[Intel-gfx] drm/i915/selftest: Remove avoidable init assignment

We can skip the assignment and i915 variable altogether and use refernce directly. Also used at single place only. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/selftests/i915_request.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests

[Intel-gfx] [Intel-gfx V2] drm/i915/selftests: Fix live_requests for all engines

commit message - Matt - Add BUG_ON to match vm v3(Tejas): - Fix dim checkpatch warnings Acked-by: Andi Shyti Signed-off-by: Tvrtko Ursulin Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/selftests/i915_request.c | 133 ++ 1 file changed, 77 insertions(+), 56 del

[Intel-gfx] drm/i915/selftests: Fix live_requests for all engines

commit message - Matt - Add BUG_ON to match vm Acked-by: Andi Shyti Signed-off-by: Tvrtko Ursulin Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/selftests/i915_request.c | 133 ++ 1 file changed, 77 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/sel

[Intel-gfx] [PATCH] drm/i915/ehl: Update MOCS table for EHL

e MOCS table for EHL"") Signed-off-by: Matt Roper Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_mocs.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index c6ebe2781076..152244d

[Intel-gfx] [PATCH V2] drm/i915/rpl-p: Add PCI IDs

Tolakanahalli Pradeep Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.c | 9 + drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915/rpl-p: Add PCI IDs

From: Matt Atwood Adding initial PCI ids for RPL-P. RPL-P behaves identically to ADL-P from i915's point of view. Bspec: 55376 Signed-off-by: Matt Atwood Signed-off-by: Madhumitha Tolakanahalli Pradeep Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1

[Intel-gfx] [PATCH] drm/i915/adl-n: Differentiate ADLP and ADLN steppings

ADL-N and ADL-P stepping are different, thus we need to add check for ADL-N in IS_ADLP_DISPLAY_STEP(). Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915

[Intel-gfx] [topic/core-for-CI] dma-buf: Check for empty dma_fence_array

Signed-off-by: Christian König Signed-off-by: Tejas Upadhyay --- drivers/dma-buf/dma-fence-array.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/dma-buf/dma-fence-array.c b/drivers/dma-buf/dma-fence-array.c index 52b85d292383..5c8a7084577b 100644 --- a/drivers/dma-buf/dma

[Intel-gfx] [PATCH] drm/i915: Add RPL-S PCI IDs

Add couple of RPL-S device ids Bspec : 53655 Cc: Matt Roper Signed-off-by: Tejas Upadhyay --- include/drm/i915_pciids.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 3609f3254f24..638be9cddba4 100644

[Intel-gfx] [PATCH 2/2] drm/i915/gt: preempt and reset based on reset domain

When we have shared reset domains, as we the engine may be indirectly coupled to the stalled engine, and we need to idle the current context to prevent collateral damage. Suggested-by: Chris Wilson Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_engine.h | 3

[Intel-gfx] [PATCH 1/2] drm/i915/gt: preempt engine to idle before reset

of the context switch into the preemption context, we know the existing contexts are now idle. This is useful for reset, as it means we can proceed knowing that the engine is idle or hung (and so needs a reset). Suggested-by: Chris Wilson Signed-off-by: Chris Wilson Signed-off-by: Tejas Upadhyay

[Intel-gfx] [PATCH] drm/i915/adl-n: Add stepping info

Add ADL-N stepping-substepping info in accordance to BSpec. Bspec: 68397 Cc: Matt Roper Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/intel_step.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index

[Intel-gfx] [PATCH] iommu/vt-d: Add RPLS to quirk list to skip TE disabling

for those devices and skips TE disabling if the qurik hits. Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4898 Tested-by: Raviteja Goud Talla Cc: Rodrigo Vivi Acked-by: Lu Baolu Signed-off-by: Tejas Upadhyay --- drivers/iommu/intel/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH topic/core-for-CI] PCI: vmd: Prevent recursive locking on interrupt allocation

From: Thomas Gleixner Tejas reported the following recursive locking issue: swapper/0/1 is trying to acquire lock: 8881074fd0a0 (>mutex){+.+.}-{3:3}, at: msi_get_virq+0x30/0xc0 but task is already holding lock: 8881017cd6a0 (>mutex){+.+.}-{3:3}, at:

[Intel-gfx] [PATCH topic/core-for-CI] iommu/vt-d: Add RPLS to quirk list to skip TE disabling

for those devices and skips TE disabling if the qurik hits. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4898 Tested-by: Raviteja Goud Talla Reviewed-by: Rodrigo Vivi Signed-off-by: Tejas Upadhyay --- drivers/iommu/intel/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[Intel-gfx] [PATCH V3 3/3] drm/i915: Refine VT-d scanout workaround

-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +- drivers/gpu/drm/i915/i915_gem_gtt.h| 1 + drivers/gpu/drm/i915/i915_vma.c| 9 4 files changed, 24

[Intel-gfx] [PATCH V3 2/3] drm/i915: Introduce guard pages to i915_vma

-by: Chris Wilson Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 -- drivers/gpu/drm/i915/i915_vma.c | 25 - drivers/gpu/drm/i915/i915_vma.h | 5 +++-- drivers/gpu/drm/i915/i915_vma_types.h | 3 ++- 4 files changed, 37

[Intel-gfx] [PATCH V3 1/3] drm/i915: Wrap all access to i915_vma.node.start|size

rapper. The notable exceptions are the selftests that are testing exact behaviour of i915_vma_pin/i915_vma_insert. Changes since V2 : - Rebased on drm-tip Signed-off-by: Chris Wilson Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_dpt.c | 7 ++-- drivers/g

[Intel-gfx] [PATCH V3 0/3] Replace VT-d workaround with guard pages

Replace filling the GGTT entirely with scratch pages to avoid invalid accesses from VT-d overfetch of scanout by only surrounding scanout vma with guard pages. This eliminates the 100+ms delay in resume where we have to repopulate the GGTT with scratch. This should also help in avoiding slow

[Intel-gfx] [PATCH] drm/i915/gt: use get_reset_domain() helper

We dont need to implement reset_domain in intel_engine _setup(), but can be done as a helper. Implemented as engine->reset_domain = get_reset_domain(). Cc: Rodrigo Vivi Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 74 +-- 1 file changed,

[Intel-gfx] [PATCH] iommu/vt-d: Add RPLS to quirk list to skip TE disabling

for those devices and skips TE disabling if the qurik hits. Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/4898 Fixes: LCK-10789 Tested-by: Raviteja Goud Talla Cc: Ashok Raj Cc: sta...@vger.kernel.org Signed-off-by: Tejas Upadhyay --- drivers/iommu/intel/iommu.c | 2 +- 1 file changed

[Intel-gfx] [PATCH] drm/i915/adl-n: Add PCH Support for Alder Lake N

Add the PCH ID for ADL-N. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/intel_pch.c | 1 + drivers/gpu/drm/i915/intel_pch.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index da8f82c2342f..4f7a61d5502e 100644

[Intel-gfx] [PATCH] drm/i915/gt: reset RING_HEAD during intel_gt_unset_wedged

and will reset the kernel_contexts on waking up). In the future though, this will present an issue for PCI error recovery. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 drivers/gpu/drm/i915/gt/intel_reset.c | 3 +++ 2 files changed, 11 insertions(+) diff

[Intel-gfx] [PATCH V3] drm/i915/adl-n: Enable ADL-N platform

Adding PCI device ids and enabling ADL-N platform. ADL-N from i915 point of view is subplatform of ADL-P. BSpec: 68397 Changes since V2: - Added version log history Changes since V1: - replace IS_ALDERLAKE_N with IS_ADLP_N - Jani Nikula Signed-off-by: Tejas Upadhyay --- arch

[Intel-gfx] [PATCH V2] drm/i915/adl-n: Enable ADL-N platform

Adding PCI device ids and enabling ADL-N platform. ADL-N from i915 point of view is subplatform of ADL-P. BSpec: 68397 Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 1

[Intel-gfx] [PATCH] drm/i915/gt: prepare reset based on reset domain

care of it. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 9 + drivers/gpu/drm/i915/gt/intel_reset.c| 12 ++-- drivers/gpu/drm/i915/gt/intel_reset.h| 1 + 3 files changed, 20 insertions(+), 2 deletions

[Intel-gfx] [PATCH V2] drm/i915/gt: Use hw_engine_masks as reset_domains

We need a way to reset engines by their reset domains. This change sets up way to fetch reset domains of each engine globally. Changes since V1: - Use static reset domain array - Ville and Tvrtko - Use BUG_ON at appropriate place - Tvrtko Signed-off-by: Tejas Upadhyay

[Intel-gfx] [PATCH] drm/i915/gt: Use hw_engine_masks as reset_domains

We need a way to reset engines by their reset domains. This change sets up way to fetch reset domains of each engine globally. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_engine_cs.c| 24 +++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + drivers/gpu

[Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround

that a full tile row around the vma is included with the guard. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Matthew Auld Cc: Imre Deak Reviewed-by: Matthew Auld Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++ drivers/gpu/drm/i915/gt/intel_ggtt.c

[Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma

-by: Chris Wilson Cc: Matthew Auld Reviewed-by: Matthew Auld Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++-- drivers/gpu/drm/i915/i915_vma.c | 26 +- drivers/gpu/drm/i915/i915_vma.h | 5 +++-- drivers/gpu/drm/i915

[Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size

rapper. The notable exceptions are the selftests that are testing exact behaviour of i915_vma_pin/i915_vma_insert. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_dpt.c | 4 +-- drivers/gpu/drm/i915/d

[Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages

Replace filling the GGTT entirely with scratch pages to avoid invalid accesses from VT-d overfetch of scanout by only surrounding scanout vma with guard pages. This eliminates the 100+ms delay in resume where we have to repopulate the GGTT with scratch. This should also help in avoiding slow

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

that a full tile row around the vma is included with the guard. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Matthew Auld Cc: Imre Deak Reviewed-by: Matthew Auld Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++ drivers/gpu/drm/i915/gt/intel_ggtt.c

[Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size

rapper. The notable exceptions are the selftests that are testing exact behaviour of i915_vma_pin/i915_vma_insert. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_dpt.c | 4 +-- drivers/gpu/drm/i915/d

[Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma

-by: Chris Wilson Cc: Matthew Auld Reviewed-by: Matthew Auld Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++-- drivers/gpu/drm/i915/i915_vma.c | 26 +- drivers/gpu/drm/i915/i915_vma.h | 5 +++-- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages

Replace filling the GGTT entirely with scratch pages to avoid invalid accesses from VT-d overfetch of scanout by only surrounding scanout vma with guard pages. This eliminates the 100+ms delay in resume where we have to repopulate the GGTT with scratch. This should also help in avoiding slow

[Intel-gfx] [PATCH] drm/i915/adl-n: Enable ADL-N platform

Adding PCI device ids and enabling ADL-N platform. ADL-N from i915 point of view is subplatform of ADL-P. BSpec: 68397 Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 1

[Intel-gfx] [PATCH] drm/i915/pxp: Trybot - run CI with PXP and MEI_PXP enabled

Please do not merge this is trybot patch to run CI with PXP and MEI PXP enabled to get premegre results for https://patchwork.freedesktop.org/series/96658/#rev3 change. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/Kconfig.debug | 2 ++ drivers/gpu/drm/i915/gt/intel_gt_pm.c

[Intel-gfx] [PATCH V4] drm/i915/gt: Hold RPM wakelock during PXP suspend

Remove boolean in intel_pxp_runtime_preapre for non-pxp configs. Solves build error Changes since V2 : - Open-code intel_pxp_runtime_suspend - Daniele - Remove boolean in intel_pxp_runtime_preapre - Daniele Changes since V1 : - split the HW access parts in gt_suspend_late - Daniele

[Intel-gfx] [PATCH V3] drm/i915/gt: Hold RPM wakelock during PXP suspend

_runtime_suspend - Daniele - Remove boolean in intel_pxp_runtime_preapre - Daniele Changes since V1 : - split the HW access parts in gt_suspend_late - Daniele - Remove default PXP configs Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_gt_pm.

[Intel-gfx] [PATCH V2] drm/i915/gt: Hold RPM wakelock during PXP suspend

70ee0 <4> [154.178682] PKRU: 5554 <4> [154.178687] Call Trace: <4> [154.178706] intel_pxp_fini_hw+0x23/0x30 [i915] <4> [154.179284] intel_pxp_suspend+0x1f/0x30 [i915] <4> [154.179807] live_gt_resume+0x5b/0x90 [i915] Changes since V1 : - split the HW acce

[Intel-gfx] [PATCH V2 1/2] drm/i915/pxp: run CI with PXP and MEI_PXP enabled.

By default it will be off in normal builds. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/Kconfig.debug | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index e7fd3e76f8a2..fa181693184b 100644 --- a/drivers

[Intel-gfx] [PATCH V2 2/2] drm/i915/gt: Hold RPM wakelock during PXP suspend

70ee0 <4> [154.178682] PKRU: 5554 <4> [154.178687] Call Trace: <4> [154.178706] intel_pxp_fini_hw+0x23/0x30 [i915] <4> [154.179284] intel_pxp_suspend+0x1f/0x30 [i915] <4> [154.179807] live_gt_resume+0x5b/0x90 [i915] Signed-off-by: Tejas Upadhyay --- dr

[Intel-gfx] [PATCH V2 0/2] Enable PXP support

There are recent tests added in IGT which tests PXP. As PXP not enabled by default CI is skipping the tests. This patch series : 1. Enables PXP 2. Fixes the crash occures(RPM wakelock not acquired) after enabling PXP Tejas Upadhyay (2): drm/i915/pxp: run CI with PXP and MEI_PXP enabled. drm

[Intel-gfx] [PATCH] drm/i915/pxp: run CI with PXP and MEI_PXP enabled.

By default it will be off in normal builds. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/Kconfig.debug | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index e7fd3e76f8a2..fa181693184b 100644 --- a/drivers

[Intel-gfx] [PATCH V7] drm/i915/gen11: Disable cursor clock gating in HDR mode

WA - Removed WA needed check - Added cursor plane active check - Once WA enable, software will not disable Changes since V1: - Modified way CLKGATE_DIS_PSL bit 28 was modified Reviewed-by: Ville Syrjälä Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH V6] drm/i915/gen11: Disable cursor clock gating in HDR mode

, software will not disable Changes since V1: - Modified way CLKGATE_DIS_PSL bit 28 was modified Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_display.c | 31 drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 32 insertions(+) diff

[Intel-gfx] [PATCH V5] drm/i915/gen11: Disable cursor clock gating in HDR mode

CLKGATE_DIS_PSL bit 28 was modified Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_display.c | 36 drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 37 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [PATCH] drm/i915: Remove warning from the rps worker

ed. Fixes: 4e5c8a99e1cb ("drm/i915: Drop i915_request.lock requirement for intel_rps_boost()") Reviewed-by: Chris Wilson Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_rps.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/dri

[Intel-gfx] [PATCH] drm/i915/display: Add HDR mode helper function

Add helper function with returns if HDR mode in on Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH V3] drm/i915/adl_s: Update ADL-S PCI IDs

Sync PCI IDs with Bspec. Bspec:53655 Changes since V2: - Upstream devices which are "POR" yes and "Ok to upstream" yes - James Asmus Changes since V1: - All POR and Non POR Ids needs to be upstreamed - James Asmus Signed-off-by: Tejas Upadhy

[Intel-gfx] [PATCH V2] drm/i915/adl_s: Update ADL-S PCI IDs

Sync PCI IDs with Bspec. Bspec:53655 Changes since V1: - All POR and Non POR Ids needs to be upstreamed - James Asmus Signed-off-by: Tejas Upadhyay --- include/drm/i915_pciids.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b

[Intel-gfx] [PATCH] drm/i915/adl_s: Update ADL-S PCI IDs

Sync PCI IDs with Bspec. Bspec:53655 Signed-off-by: Tejas Upadhyay --- include/drm/i915_pciids.h | 4 1 file changed, 4 deletions(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index eee18fa53b54..8adb058dfc5a 100644 --- a/include/drm/i915_pciids.h +++ b/include

[Intel-gfx] [PATCH V3] drm/i915/adl_s: Fix dma_mask_size to 39 bit

Changes since V1 : - Added more details to commit message - Matthew Auld Signed-off-by: Tejas Upadhyay Acked-by: Matthew Auld --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH V2] drm/i915/adl_s: Fix dma_mask_size to 39 bit

message - Matthew Auld Signed-off-by: Tejas Upadhyay Acked-by: Matthew Auld --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a7bfdd827bc8..0fea4c0c6d48 100644

[Intel-gfx] [PATCH] drm/i915/adl_s: Fix dma_mask_size to 39 bit

--r linear-32bpp-rotate-0 Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a7bfdd827bc8..0fea4c0c6d48 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/vgem: Use 256B aligned pitch

Having different alignment requirement by different drivers, 256B aligned should work for all drm drivers. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/vgem/vgem_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem

[Intel-gfx] [PATCH] drm/i915/jsl: Remove require_force_probe protection

/drmtip.html? Cc: Chris Wilson Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/i915_pci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index f1f43192f9fb..bc3c14ce92f7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers

[Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe protection

/drmtip.html? Cc: Chris Wilson Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/i915_pci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index f1f43192f9fb..7d472611a190 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers

[Intel-gfx] [PATCH V2] drm/i915/selftest: Extend ctx_timestamp ICL workaround to GEN11

EHL and JSL are also observing requirement for 80ns interval for CTX_TIMESTAMP thus extending it to GEN11. Changes since V1: - IS_GEN replaced by GRAPHICS_VER - Tvrtko Acked-by: Tvrtko Ursulin Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 4 ++-- 1

[Intel-gfx] [PATCH] drm/i915/selftest: Extend ctx_timestamp ICL workaround to GEN11

EHL and JSL are also observing requirement for 80ns interval for CTX_TIMESTAMP thus extending it to GEN11. Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt

[Intel-gfx] [PATCH V4] drm/i915/gen11: Disable cursor clock gating in HDR mode

plane active check - Once WA enable, software will not disable Changes since V1: - Modified way CLKGATE_DIS_PSL bit 28 was modified Cc: Souza Jose Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_display.c | 27 drivers/gpu/drm/i915

[Intel-gfx] [PATCH V2] drm/i915/ehl: Update MOCS table for EHL

From: Matt Roper These extra EHL entries were not behaving as expected without proper flushing implemented in kernel. Commit a679f58d0510 ("drm/i915: Flush pages on acquisition") introduces proper flushing to make it work as expected. Hence adding those EHL entries back. Changes since V1:

[Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock gating in HDR mode

cursor plane active check - Once WA enable, software will not disable Changes since V1: - Modified way CLKGATE_DIS_PSL bit 28 was modified Cc: Souza Jose Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_display.c | 15 +++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH V6] drm/i915/jsl: Add W/A 1409054076 for JSL

check clear flag - Add WA_verify hook in dsi sync_state Changes since V2: - Used REG_BIT, ignored pipe A and used sw state check - Jani - Made function wrapper - Jani Changes since V1: - ./dim checkpatch errors addressed Signed-off-by: Tejas Upadhyay Reviewed

[Intel-gfx] [PATCH] drm/i915/ehl: Update MOCS table for EHL

From: Matt Roper These extra EHL entries were not behaving as expected without proper flushing implemented in kernel. https://cgit.freedesktop.org/drm-tip/commit/?id=a679f58d051025db6fa86226c4d35650b75e990f patch introduces proper flushing to make it work as expected. Hence adding those EHL

[Intel-gfx] [PATCH V5] drm/i915/jsl: Add W/A 1409054076 for JSL

, ignored pipe A and used sw state check - Jani - Made function wrapper - Jani Changes since V1: - ./dim checkpatch errors addressed Cc: Imre Deak Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/icl_dsi.c | 44 ++ drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH] drm/i915/gen11: use ffs for minconfig slice/subslice

/i915: Apply Wa_1406680159:icl,ehl as an engine workaround") Cc: Mika Kuoppala Cc: Matt Roper Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +++--- drivers/gpu/drm/i915/intel_pm.c | 10 +++--- 2 files changed, 18 insertions(+), 6

[Intel-gfx] [PATCH] Revert "drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround"

This reverts commit fb899dd8ea9c4ac5928b86946e6536790981adae. w/a on mentioned platforms not working as expected and causing more harm on the RC6 flow. Fixes: fb899dd8ea9c ("drm/i915: Apply Wa_1406680159:icl,ehl as an engine workaround") Cc: Mika Kuoppala Cc: Matt Roper Signed-off

[Intel-gfx] [PATCH V4] drm/i915/jsl: Add W/A 1409054076 for JSL

addressed Cc: Imre Deak Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/icl_dsi.c | 45 ++ drivers/gpu/drm/i915/i915_reg.h| 1 + 2 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

in cc - Added patch ref in commit message V1: - Added Cc: x...@kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: x...@kernel.org Cc: José Roberto de Souza Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + 1 file

[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

in cc - Added patch ref in commit message V1: - Added Cc: x...@kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: x...@kernel.org Cc: José Roberto de Souza Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + 1 file

[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

in cc - Added patch ref in commit message V1: - Added Cc: x...@kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: x...@kernel.org Cc: José Roberto de Souza Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + 1 file

[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

in cc - Added patch ref in commit message V1: - Added Cc: x...@kernel.org Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: x...@kernel.org Cc: José Roberto de Souza Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + 1 file

[Intel-gfx] [PATCH V2] x86/gpu: add JasperLake to gen11 early quirks

Let's reserve JSL stolen memory for graphics. JasperLake is a gen11 platform which is compatible with ICL/EHL changes. V1: - Added Cc: x...@kernel.org Cc: x...@kernel.org Signed-off-by: Tejas Upadhyay --- arch/x86/kernel/early-quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git

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