v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
v4 : Fix feedfwd gain (Ville)
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
Signed-off-by: Ville Syrjala ville.syrj...@linux.intel.com
is enabled (Ville)
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
Signed-off-by: Ville Syrjala ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |9 +
2 files changed, 10 insertions(+)
diff --git
those bits as part of RMW.
v4: TDC target cnt is 10 bits and not 8 bits (Ville)
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files
of RMW
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 13 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
those bits as part of RMW.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files changed, 33 insertions(+), 12 deletions(-)
diff --git
Initialize lock detect threshold and select coarse threshold if M2 is
zero
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 42
As per the recommendation from PHY team, limit the max vco supported in CHV to
6.48 GHz
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
Handle M2 frac division for both M2 frac and int cases
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915
Added new PHY register definitions to control TDC buffer calibration and
digital lock threshold.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915
Changes since version 1:
Addressed Ville's review comments
Decoded the magic numbers as much as possible
Split the single patch into logical patch set
Dropped the DPIO_CLK_EN changes
Vijay Purushothaman (5):
drm/i915: Add new PHY reg definitions for lock
This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity issues for both HDMI and DP.
Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
Signed-off-by: Vijay Purushothaman
));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void i9xx_update_wm(struct drm_crtc *unused_crtc)
Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
___
Intel-gfx mailing list
Intel-gfx
explained above.
*/
- if (IS_GEN2(dev))
- intel_wait_for_vblank(dev, pipe);
+ intel_wait_for_vblank(dev, pipe);
intel_disable_pipe(dev_priv, pipe);
Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
, things are clear for me.
For the series,
Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Thanks,
Vijay
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
= NULL;
+ if (!HAS_PSR(dev))
+ return;
+
list_for_each_entry(encoder, dev-mode_config.encoder_list, base.head)
if (encoder-type == INTEL_OUTPUT_EDP) {
intel_dp = enc_to_intel_dp(encoder-base);
Reviewed-by: Vijay Purushothaman
;
+
list_for_each_entry(encoder, dev-mode_config.encoder_list, base.head)
if (encoder-type == INTEL_OUTPUT_EDP) {
intel_dp = enc_to_intel_dp(encoder-base);
Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
On 5/16/2014 10:12 PM, Rodrigo Vivi wrote:
On Fri, May 16, 2014 at 3:23 AM, Chris Wilson ch...@chris-wilson.co.uk
mailto:ch...@chris-wilson.co.uk wrote:
On Thu, May 15, 2014 at 08:13:05PM -0400, Rodrigo Vivi wrote:
The perfect solution for psr_exit is the hardware tracking the
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 28144d3..9421b0b 100644
---
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Now we have the active/inactive state for exit and this actually changes the
HW enable bit the status was a bit confusing for users. So let's provide
more info.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c
On 2/7/2014 9:28 PM, Ville Syrjälä wrote:
On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote:
B-spec says the FIFO total size is 512. So fix this to 512.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
1 file
On 2/6/2014 12:28 PM, Vijay Purushothaman wrote:
On 2/5/2014 10:18 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 09:25:36PM +0530, Vijay Purushothaman wrote:
On 2/5/2014 8:43 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote:
Hello,
In our
Hello,
In our current driver implementation we support flip notifications only
for primary plane. So, in a full screen video playback scenario where
only one sprite plane is active, the user space is forced to rely on
primary plane flip notification even though there is no real need for
this
On 2/5/2014 10:18 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 09:25:36PM +0530, Vijay Purushothaman wrote:
On 2/5/2014 8:43 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote:
Hello,
In our current driver implementation we support flip
On 6/28/2013 7:54 PM, Ville Syrjälä wrote:
On Fri, Jun 28, 2013 at 07:45:31PM +0530, Vijay Purushothaman wrote:
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us to get a nice
performance boost to both 3D media workloads
On 6/28/2013 9:35 PM, Chris Wilson wrote:
On Fri, Jun 28, 2013 at 05:24:50PM +0300, Ville Syrjälä wrote:
On Fri, Jun 28, 2013 at 07:45:31PM +0530, Vijay Purushothaman wrote:
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us to get a nice
performance boost to both 3D media workloads based on sprite (~60 fps
from ~20 fps)
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off
On 9/26/2012 7:54 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL
On 9/26/2012 8:08 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off
On 9/26/2012 8:10 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
From: Bhat, Gajanan gajanan.b...@intel.com
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
On 9/26/2012 8:19 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks
On 9/27/2012 12:48 PM, Jani Nikula wrote:
On Wed, 26 Sep 2012, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
This patch set enables all supported display interfaces like HDMI, DisplayPort
and eDP for Valleyview. This also enables support for multi-display
configurations.
v2: Addressed review comments from Daniel and Jani Nikula.
Gajanan Bhat (1):
drm/i915: Add eDP support for Valleyview
Vijay
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |8
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
drivers/gpu/drm/i915/intel_dp.c
Added DPIO data lane register definitions for Valleyview
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 90
Temporary work around to avoid spurious crt hotplug interrupts.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_crt.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm
interfaces
v4: removed unconditional enabling of 6bpc dithering based on comments
from Daniel Jani Nikula. Also changed the display enabling order to
force eDP detection first.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Fixed correct min, max vco limits and dip ctl reg
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915
?
Bhat, Gajanan (1):
drm/i915: Enable multi display support in VLV
Vijay Purushothaman (8):
drm/i915: Set aux clk to 100MHz for Valleyview
drm/i915: Fix SDVO IER and status bits for Valleyview
drm/i915: Add Valleyview lane control definitions
drm/i915: Program correct m n tu register
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |8
Added DPIO data lane register definitions for Valleyview
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL sequence.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915
Bhat gajanan.b...@intel.com
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |6 ++
drivers/gpu/drm/i915/intel_dp.c | 13 -
2 files changed, 14 insertions
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm
From: Bhat, Gajanan gajanan.b...@intel.com
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, extended desktop) should work for VLV.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
in progress for Valleyview. So, i did not
test the combinations like VGA+HDMI or VGA+DP.
Tested-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Acked-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Thanks,
Vijay
Daniel Vetter (58):
drm/i915: add crtc-enable/disable vfuncs insted
the wrong bits and field definitions.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
---
drivers/gpu/drm/i915/intel_sprite.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
This is already fixed for ILK and SNB but somehow IVB is missed.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Lin ben.y@intel.com
---
drivers/gpu/drm/i915/intel_sprite.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
and field definitions.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Lin ben.y@intel.com
---
drivers/gpu/drm/i915/intel_sprite.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu
On 8/22/2012 1:19 PM, Paul Menzel wrote:
Dear Vijay,
Am Mittwoch, den 22.08.2012, 11:47 +0530 schrieb Vijay Purushothaman:
This is already fixed for ILK and SNB
… in what commits?
Added the previous commit number which solved this problem on
Sandybridge and description in the second version
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman
On Thu, 2 Aug 2012 09:06:48 -0700
Ben Widawsky b...@bwidawsk.net wrote:
On 2012-08-02 05:07, Vijay Purushothaman wrote:
In Valleyview the DPLL and lane control registers are accessible
only through side band fabric called DPIO. Added two tools to read
and write
registers residing
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
---
tools/Makefile.am|2 +
tools
refactoring, most welcome!
Thanks,
Vijay
Vijay Purushothaman (2):
drm/i915 : fix incorrect p2 values for Valleyview
drm/i915: cleanup Valleyview PLL calculation
drivers/gpu/drm/i915/intel_display.c | 58 ++
1 files changed, 24 insertions(+), 34 deletions
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 157dcb0a..0707b7a 100644
replaced hardcoded numbers with valid PLL limit values
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 52 +
1 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915
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