[Intel-gfx] [v2 4/5] drm/i915: Initialize CHV digital lock detect threshold

[Vijay Purushothaman]

Initialize lock detect threshold and select coarse threshold if M2 is
zero

Signed-off-by: Vijay Purushothaman <vijay.a.purushotha...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 87d1721..ae2a77f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6085,11 +6085,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
                dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
                vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
 
+               /* Program digital lock detect threshold */
+               dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+               dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+               vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
        } else {
                /* M2 fraction division disable */
                dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
                dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
                vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+               /* Program digital lock detect threshold */
+               dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+               dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+               dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+               vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
        }
 
        /* Loop filter */
-- 
1.7.9.5

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