Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add Wa_2201832410

2018-04-11 Thread Mika Kuoppala 
Rodrigo Vivi  writes:

> "Clock gating bug in GWL may not clear barrier state when an EOT
> is received, causing a hang the next time that barrier is used."
>
> HSDES: 2201832410
>

A bit late here but do we have a preference of going like
the above or,

References: HSDES#2201832410

?
-Mika


> Cc: Rafael Antognolli 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4787d9bf58b9..e6a8c0ee7df1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3965,6 +3965,9 @@ enum {
>  #define  SARBUNIT_CLKGATE_DIS(1 << 5)
>  #define  RCCUNIT_CLKGATE_DIS (1 << 7)
>  
> +#define SUBSLICE_UNIT_LEVEL_CLKGATE  _MMIO(0x9524)
> +#define  GWUNIT_CLKGATE_DIS  (1 << 16)
> +
>  #define UNSLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x9434)
>  #define  VFUNIT_CLKGATE_DIS  (1 << 20)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6cab20ce167a..b8da4dcdd584 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>   val |= SARBUNIT_CLKGATE_DIS;
>   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
>  
> + /* Wa_2201832410:cnl */
> + val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
> + val |= GWUNIT_CLKGATE_DIS;
> + I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> +
>   /* WaDisableVFclkgate:cnl */
>   /* WaVFUnitClockGatingDisable:cnl */
>   val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
> -- 
> 2.13.6
>
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add Wa_2201832410

2018-03-08 Thread Rodrigo Vivi 
On Thu, Mar 08, 2018 at 12:30:07PM +0200, Jani Nikula wrote:
> On Wed, 07 Mar 2018, Rodrigo Vivi  wrote:
> > On Wed, Mar 07, 2018 at 02:48:05PM -0800, Rafael Antognolli wrote:
> >> Matches bspec.
> >> 
> >> Reviewed-by: Rafael Antognolli 
> >
> > pushed, thanks
> 
> Okay, too late now, but I think "Add Wa_2201832410" as a commit title is
> insufficient. Even a few words around it about the change would be
> appreciated.

yeap... good point.

usually wa names had some WaSomeInformationOnName and I got used to only
use that as subject... This round of Wa came only with HSD number on it.
But we should be able to add few useful information on subject indeed.

Noted for next Wa_<#hsdesnumber>

thanks for the feedback.

> 
> Thanks,
> Jani.
> 
> 
> >
> >> 
> >> On Wed, Mar 07, 2018 at 02:09:12PM -0800, Rodrigo Vivi wrote:
> >> > "Clock gating bug in GWL may not clear barrier state when an EOT
> >> > is received, causing a hang the next time that barrier is used."
> >> > 
> >> > HSDES: 2201832410
> >> > 
> >> > Cc: Rafael Antognolli 
> >> > Signed-off-by: Rodrigo Vivi 
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_reg.h | 3 +++
> >> >  drivers/gpu/drm/i915/intel_pm.c | 5 +
> >> >  2 files changed, 8 insertions(+)
> >> > 
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> >> > b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 4787d9bf58b9..e6a8c0ee7df1 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -3965,6 +3965,9 @@ enum {
> >> >  #define  SARBUNIT_CLKGATE_DIS   (1 << 5)
> >> >  #define  RCCUNIT_CLKGATE_DIS(1 << 7)
> >> >  
> >> > +#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> >> > +#define  GWUNIT_CLKGATE_DIS (1 << 16)
> >> > +
> >> >  #define UNSLICE_UNIT_LEVEL_CLKGATE  _MMIO(0x9434)
> >> >  #define  VFUNIT_CLKGATE_DIS (1 << 20)
> >> >  
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> >> > b/drivers/gpu/drm/i915/intel_pm.c
> >> > index 6cab20ce167a..b8da4dcdd584 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
> >> > drm_i915_private *dev_priv)
> >> >  val |= SARBUNIT_CLKGATE_DIS;
> >> >  I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
> >> >  
> >> > +/* Wa_2201832410:cnl */
> >> > +val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
> >> > +val |= GWUNIT_CLKGATE_DIS;
> >> > +I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> >> > +
> >> >  /* WaDisableVFclkgate:cnl */
> >> >  /* WaVFUnitClockGatingDisable:cnl */
> >> >  val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
> >> > -- 
> >> > 2.13.6
> >> > 
> > ___
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> 
> -- 
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add Wa_2201832410

2018-03-08 Thread Jani Nikula 
On Wed, 07 Mar 2018, Rodrigo Vivi  wrote:
> On Wed, Mar 07, 2018 at 02:48:05PM -0800, Rafael Antognolli wrote:
>> Matches bspec.
>> 
>> Reviewed-by: Rafael Antognolli 
>
> pushed, thanks

Okay, too late now, but I think "Add Wa_2201832410" as a commit title is
insufficient. Even a few words around it about the change would be
appreciated.

Thanks,
Jani.


>
>> 
>> On Wed, Mar 07, 2018 at 02:09:12PM -0800, Rodrigo Vivi wrote:
>> > "Clock gating bug in GWL may not clear barrier state when an EOT
>> > is received, causing a hang the next time that barrier is used."
>> > 
>> > HSDES: 2201832410
>> > 
>> > Cc: Rafael Antognolli 
>> > Signed-off-by: Rodrigo Vivi 
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> >  drivers/gpu/drm/i915/intel_pm.c | 5 +
>> >  2 files changed, 8 insertions(+)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> > b/drivers/gpu/drm/i915/i915_reg.h
>> > index 4787d9bf58b9..e6a8c0ee7df1 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -3965,6 +3965,9 @@ enum {
>> >  #define  SARBUNIT_CLKGATE_DIS (1 << 5)
>> >  #define  RCCUNIT_CLKGATE_DIS  (1 << 7)
>> >  
>> > +#define SUBSLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x9524)
>> > +#define  GWUNIT_CLKGATE_DIS   (1 << 16)
>> > +
>> >  #define UNSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9434)
>> >  #define  VFUNIT_CLKGATE_DIS   (1 << 20)
>> >  
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>> > b/drivers/gpu/drm/i915/intel_pm.c
>> > index 6cab20ce167a..b8da4dcdd584 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
>> > drm_i915_private *dev_priv)
>> >val |= SARBUNIT_CLKGATE_DIS;
>> >I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
>> >  
>> > +  /* Wa_2201832410:cnl */
>> > +  val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
>> > +  val |= GWUNIT_CLKGATE_DIS;
>> > +  I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
>> > +
>> >/* WaDisableVFclkgate:cnl */
>> >/* WaVFUnitClockGatingDisable:cnl */
>> >val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
>> > -- 
>> > 2.13.6
>> > 
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add Wa_2201832410

2018-03-07 Thread Rodrigo Vivi 
On Wed, Mar 07, 2018 at 02:48:05PM -0800, Rafael Antognolli wrote:
> Matches bspec.
> 
> Reviewed-by: Rafael Antognolli 

pushed, thanks

> 
> On Wed, Mar 07, 2018 at 02:09:12PM -0800, Rodrigo Vivi wrote:
> > "Clock gating bug in GWL may not clear barrier state when an EOT
> > is received, causing a hang the next time that barrier is used."
> > 
> > HSDES: 2201832410
> > 
> > Cc: Rafael Antognolli 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 3 +++
> >  drivers/gpu/drm/i915/intel_pm.c | 5 +
> >  2 files changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4787d9bf58b9..e6a8c0ee7df1 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3965,6 +3965,9 @@ enum {
> >  #define  SARBUNIT_CLKGATE_DIS  (1 << 5)
> >  #define  RCCUNIT_CLKGATE_DIS   (1 << 7)
> >  
> > +#define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
> > +#define  GWUNIT_CLKGATE_DIS(1 << 16)
> > +
> >  #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
> >  #define  VFUNIT_CLKGATE_DIS(1 << 20)
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 6cab20ce167a..b8da4dcdd584 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
> > drm_i915_private *dev_priv)
> > val |= SARBUNIT_CLKGATE_DIS;
> > I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
> >  
> > +   /* Wa_2201832410:cnl */
> > +   val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
> > +   val |= GWUNIT_CLKGATE_DIS;
> > +   I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> > +
> > /* WaDisableVFclkgate:cnl */
> > /* WaVFUnitClockGatingDisable:cnl */
> > val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
> > -- 
> > 2.13.6
> > 
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add Wa_2201832410

2018-03-07 Thread Rafael Antognolli 
Matches bspec.

Reviewed-by: Rafael Antognolli 

On Wed, Mar 07, 2018 at 02:09:12PM -0800, Rodrigo Vivi wrote:
> "Clock gating bug in GWL may not clear barrier state when an EOT
> is received, causing a hang the next time that barrier is used."
> 
> HSDES: 2201832410
> 
> Cc: Rafael Antognolli 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4787d9bf58b9..e6a8c0ee7df1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3965,6 +3965,9 @@ enum {
>  #define  SARBUNIT_CLKGATE_DIS(1 << 5)
>  #define  RCCUNIT_CLKGATE_DIS (1 << 7)
>  
> +#define SUBSLICE_UNIT_LEVEL_CLKGATE  _MMIO(0x9524)
> +#define  GWUNIT_CLKGATE_DIS  (1 << 16)
> +
>  #define UNSLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x9434)
>  #define  VFUNIT_CLKGATE_DIS  (1 << 20)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6cab20ce167a..b8da4dcdd584 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>   val |= SARBUNIT_CLKGATE_DIS;
>   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
>  
> + /* Wa_2201832410:cnl */
> + val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
> + val |= GWUNIT_CLKGATE_DIS;
> + I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> +
>   /* WaDisableVFclkgate:cnl */
>   /* WaVFUnitClockGatingDisable:cnl */
>   val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
> -- 
> 2.13.6
> 
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[Intel-gfx] [PATCH] drm/i915/cnl: Add Wa_2201832410

2018-03-07 Thread Rodrigo Vivi 
"Clock gating bug in GWL may not clear barrier state when an EOT
is received, causing a hang the next time that barrier is used."

HSDES: 2201832410

Cc: Rafael Antognolli 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4787d9bf58b9..e6a8c0ee7df1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3965,6 +3965,9 @@ enum {
 #define  SARBUNIT_CLKGATE_DIS  (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS   (1 << 7)
 
+#define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
+#define  GWUNIT_CLKGATE_DIS(1 << 16)
+
 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
 #define  VFUNIT_CLKGATE_DIS(1 << 20)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6cab20ce167a..b8da4dcdd584 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
drm_i915_private *dev_priv)
val |= SARBUNIT_CLKGATE_DIS;
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
 
+   /* Wa_2201832410:cnl */
+   val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
+   val |= GWUNIT_CLKGATE_DIS;
+   I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
+
/* WaDisableVFclkgate:cnl */
/* WaVFUnitClockGatingDisable:cnl */
val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
-- 
2.13.6

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[Intel-gfx] [PATCH] drm/i915/cnl: Add Wa_2201832410

2018-03-05 Thread Rodrigo Vivi 
"Clock gating bug in GWL may not clear barrier state when an EOT
is received, causing a hang the next time that barrier is used."

HSDES: 2201832410

Cc: Rafael Antognolli 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a060726fed7e..42baf90edb6f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3953,6 +3953,9 @@ enum {
 #define  SARBUNIT_CLKGATE_DIS  (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS   (1 << 7)
 
+#define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
+#define  GWUNIT_CLKGATE_DIS(1 << 16)
+
 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
 #define  VFUNIT_CLKGATE_DIS(1 << 20)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3e60279f18b1..be01012bb65f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
drm_i915_private *dev_priv)
val |= SARBUNIT_CLKGATE_DIS;
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
 
+   /* Wa_2201832410:cnl */
+   val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
+   val |= GWUNIT_CLKGATE_DIS;
+   I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
+
/* WaDisableVFclkgate:cnl */
val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
val |= VFUNIT_CLKGATE_DIS;
-- 
2.13.6

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