On Thu, 2017-08-31 at 11:27 +0300, Joonas Lahtinen wrote:
> On Wed, 2017-08-30 at 17:58 +, Vivi, Rodrigo wrote:
> > On Wed, 2017-08-30 at 14:38 +0300, Joonas Lahtinen wrote:
> > > On Wed, 2017-08-30 at 12:26 +0100, Chris Wilson wrote:
> > > > Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> > >
On Wed, 2017-08-30 at 17:58 +, Vivi, Rodrigo wrote:
> On Wed, 2017-08-30 at 14:38 +0300, Joonas Lahtinen wrote:
> > On Wed, 2017-08-30 at 12:26 +0100, Chris Wilson wrote:
> > > Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> > > > On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > > >
On Wed, 2017-08-30 at 14:38 +0300, Joonas Lahtinen wrote:
> On Wed, 2017-08-30 at 12:26 +0100, Chris Wilson wrote:
> > Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> > > On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > > > Driver’s CPU access to GTT is via the GTTMMADR BAR.
> > > >
> >
On Wed, 2017-08-30 at 12:26 +0100, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> > On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > > Driver’s CPU access to GTT is via the GTTMMADR BAR.
> > >
> > > The current HW implementation of that BAR is to only
> > >
Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > Driver’s CPU access to GTT is via the GTTMMADR BAR.
> >
> > The current HW implementation of that BAR is to only
> > support <= DW (and maybe QW) writes—not 16/32/64B writes
> > that could
On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> Driver’s CPU access to GTT is via the GTTMMADR BAR.
>
> The current HW implementation of that BAR is to only
> support <= DW (and maybe QW) writes—not 16/32/64B writes
> that could occur with WC and/or SSE/AVX moves.
>
> GTTMMADR must be
Driver’s CPU access to GTT is via the GTTMMADR BAR.
The current HW implementation of that BAR is to only
support <= DW (and maybe QW) writes—not 16/32/64B writes
that could occur with WC and/or SSE/AVX moves.
GTTMMADR must be marked uncacheable (UC).
Accesses to GTTMMADR(GTT), must be 64 bits or
On Fri, Aug 11, 2017 at 4:39 PM, Rodrigo Vivi wrote:
> WC is apparently not an option for CNL+ on GTT here.
> Trying to use it we get hard hangs.
>
> Credits-to: Ben Widawsky
forgot to CC relavant people for possible reviews:
Cc: Joonas
Cc:
WC is apparently not an option for CNL+ on GTT here.
Trying to use it we get hard hangs.
Credits-to: Ben Widawsky
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff