Re: [Intel-gfx] [PATCH] drm/i915: workaround bad DSL readout v3

2015-09-23 Thread Jani Nikula
On Tue, 22 Sep 2015, Jesse Barnes wrote: > On HSW at least (still testing other platforms, but should be harmless > elsewhere), the DSL reg reads back as 0 when read around vblank start > time. This ends up confusing the atomic start/end checking code, since > it causes

[Intel-gfx] [PATCH] drm/i915: workaround bad DSL readout v3

2015-09-22 Thread Jesse Barnes
On HSW at least (still testing other platforms, but should be harmless elsewhere), the DSL reg reads back as 0 when read around vblank start time. This ends up confusing the atomic start/end checking code, since it causes the update to appear as if it crossed a frame count boundary. Avoid the