Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to 594000MHz modes. Add 16 Bit mask operators to support C20 phy programming.
BSPEC: 64568 Cc: Imre Deak <imre.d...@intel.com> Cc: Mika Kahola <mika.kah...@intel.com> Cc: Radhakrishna Sripada <radhakrishna.srip...@intel.com> Cc: Gustavo Sousa <gustavo.so...@intel.com> Signed-off-by: Clint Taylor <clinton.a.tay...@intel.com> Clint Taylor (2): drm/i915: Add 16bit register/mask operators drm/i915/hdmi: C20 computed PLL frequencies drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89 +++++++++++++++++-- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 53 +++++++++++ drivers/gpu/drm/i915/i915_reg_defs.h | 49 ++++++++++ 3 files changed, 185 insertions(+), 6 deletions(-) -- 2.25.1
