[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-21 Thread Vidya Srinivas
From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-14 Thread Vidya Srinivas
From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in

Re: [Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-14 Thread Sharma, Shashank
Reviewed-by: Shashank Sharma Regards Shashank On 2/14/2018 10:27 AM, Vidya Srinivas wrote: From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-13 Thread Vidya Srinivas
From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-13 Thread Vidya Srinivas
From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in

Re: [Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-07 Thread Sharma, Shashank
Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: From: Mahesh Kumar NV12 formats have two registers for DDB. Verify both the registers for NV12 during verify_wm_state. The commit message can add a little more details about how we are planning to program.

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-06 Thread Vidya Srinivas
From: Mahesh Kumar NV12 formats have two registers for DDB. Verify both the registers for NV12 during verify_wm_state. v2: Addressed review comments by Maarten. Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-02-06 Thread Vidya Srinivas
From: Mahesh Kumar NV12 formats have two registers for DDB. Verify both the registers for NV12 during verify_wm_state. v2: Addressed review comments by Maarten. Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

2018-01-22 Thread Vidya Srinivas
From: Mahesh Kumar NV12 formats have two registers for DDB. Verify both the registers for NV12 during verify_wm_state. v2: Addressed review comments by Maarten. Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas