[Intel-gfx] [PATCH 05/14] drm/i915/display: Account for DSC not split case while computing cdclk

[Ankit Nautiyal]

Currently we assume 2 Pixels Per Clock (PPC) while computing
plane cdclk and min_cdlck. In cases where DSC single engine
is used the throughput is 1 PPC.

So account for the above case, while computing cdclk.

Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 6 +++++-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 7 +++++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6bed75f1541a..14ccda8a0bf1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2494,8 +2494,12 @@ static int intel_pixel_rate_to_cdclk(const struct 
intel_crtc_state *crtc_state)
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
        int pixel_rate = crtc_state->pixel_rate;
 
+       /*
+        * If single VDSC engine is used, it uses one pixel per clock
+        * otherwise we use two pixels per clock.
+        */
        if (DISPLAY_VER(dev_priv) >= 10)
-               return DIV_ROUND_UP(pixel_rate, 2);
+               return crtc_state->dsc.dsc_split? pixel_rate : 
DIV_ROUND_UP(pixel_rate, 2);
        else if (DISPLAY_VER(dev_priv) == 9 ||
                 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
                return pixel_rate;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 110401aab038..2da43ce5c302 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -263,8 +263,11 @@ static int icl_plane_min_cdclk(const struct 
intel_crtc_state *crtc_state,
 {
        unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, 
plane_state);
 
-       /* two pixels per clock */
-       return DIV_ROUND_UP(pixel_rate, 2);
+       /*
+        * If single VDSC engine is used, it uses one pixel per clock
+        * otherwise we use two pixels per clock.
+        */
+       return crtc_state->dsc.dsc_split? pixel_rate : DIV_ROUND_UP(pixel_rate, 
2);
 }
 
 static void
-- 
2.25.1