Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-15 Thread Eugeni Dodonov
On Wed, Dec 14, 2011 at 19:33, Jesse Barnes jbar...@virtuousgeek.orgwrote: On Thu, 08 Dec 2011 18:35:24 -0800 Eric Anholt e...@anholt.net wrote: Since MI_FLUSH_DW exists on gen6, and keithp says we still have outstanding issues with missed blit IRQs there, I started trying it today. Two

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-14 Thread Jesse Barnes
On Thu, 08 Dec 2011 18:35:24 -0800 Eric Anholt e...@anholt.net wrote: Since MI_FLUSH_DW exists on gen6, and keithp says we still have outstanding issues with missed blit IRQs there, I started trying it today. Two kernel branches posted at git://people.freedesktop.org/~anholt/linux/

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-08 Thread Eric Anholt
On Wed, 7 Dec 2011 13:03:29 -0800, Jesse Barnes jbar...@virtuousgeek.org wrote: On Wed, 07 Dec 2011 12:54:07 -0800 Eric Anholt e...@anholt.net wrote: On Wed, 7 Dec 2011 11:58:05 -0800, Jesse Barnes jbar...@virtuousgeek.org wrote: On Wed, 7 Dec 2011 10:38:41 -0800 Jesse Barnes

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-07 Thread Eric Anholt
On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky b...@bwidawsk.net wrote: The docs say this is required for Gen7, and since the bit was added for Gen6, we are also setting it there pit pf paranoia. Particularly as Chris points out, if PIPE_CONTROL counts as a 3d state packet. This was found

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-07 Thread Jesse Barnes
On Wed, 07 Dec 2011 10:35:45 -0800 Eric Anholt e...@anholt.net wrote: On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky b...@bwidawsk.net wrote: The docs say this is required for Gen7, and since the bit was added for Gen6, we are also setting it there pit pf paranoia. Particularly as Chris

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-07 Thread Jesse Barnes
On Wed, 7 Dec 2011 10:38:41 -0800 Jesse Barnes jbar...@virtuousgeek.org wrote: On Wed, 07 Dec 2011 10:35:45 -0800 Eric Anholt e...@anholt.net wrote: On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky b...@bwidawsk.net wrote: The docs say this is required for Gen7, and since the bit was

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-07 Thread Eric Anholt
On Wed, 7 Dec 2011 11:58:05 -0800, Jesse Barnes jbar...@virtuousgeek.org wrote: On Wed, 7 Dec 2011 10:38:41 -0800 Jesse Barnes jbar...@virtuousgeek.org wrote: On Wed, 07 Dec 2011 10:35:45 -0800 Eric Anholt e...@anholt.net wrote: On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-12-07 Thread Jesse Barnes
On Wed, 07 Dec 2011 12:54:07 -0800 Eric Anholt e...@anholt.net wrote: On Wed, 7 Dec 2011 11:58:05 -0800, Jesse Barnes jbar...@virtuousgeek.org wrote: On Wed, 7 Dec 2011 10:38:41 -0800 Jesse Barnes jbar...@virtuousgeek.org wrote: On Wed, 07 Dec 2011 10:35:45 -0800 Eric Anholt

[Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

2011-10-22 Thread Ben Widawsky
The docs say this is required for Gen7, and since the bit was added for Gen6, we are also setting it there pit pf paranoia. Particularly as Chris points out, if PIPE_CONTROL counts as a 3d state packet. This was found through doc inspection by Ken and applies to Gen6+; Cc: Keith Packard