Re: [Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

2022-10-03 Thread Sripada, Radhakrishna 



> -Original Message-
> From: De Marchi, Lucas 
> Sent: Thursday, September 29, 2022 5:11 PM
> To: Sripada, Radhakrishna 
> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH v4.1] drm/i915/mtl: Define engine context layouts
> 
> On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote:
> >From: Matt Roper 
> >
> >The part of the media and blitter engine contexts that we care about for
> >setting up an initial state on MTL are nearly similar to DG2 (and PVC).
> >The difference being PRT_BB_STATE being replaced with NOP.
> >
> >For render/compute engines, the part of the context images are nearly
> >the same, although the layout had a very slight change --- one POSH
> >register was removed and the placement of some LRI/noops adjusted
> >slightly to compensate.
> >
> >v2:
> > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> > - Add missing nop in xcs offsets(Bala)
> >v3:
> > - Fix the spacing for nop in xcs offset(MattR)
> >v4:
> > - Fix rcs register offset(MattR)
> >v4.1:
> > - Fix commit message(Lucas)
> >
> >Bspec: 46261, 46260, 45585
> >Cc: Balasubramani Vivekanandan 
> >Cc: Licas De Marchi 
> >Signed-off-by: Matt Roper 
> >Signed-off-by: Radhakrishna Sripada 
> 
> 
> Reviewed-by: Lucas De Marchi 
Pushed the patch, Thanks for the review.

-Radhakrishna Sripada
> 
> Lucas De Marchi

Re: [Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

2022-09-29 Thread Lucas De Marchi 

On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote:

From: Matt Roper 

The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
- Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
- Add missing nop in xcs offsets(Bala)
v3:
- Fix the spacing for nop in xcs offset(MattR)
v4:
- Fix rcs register offset(MattR)
v4.1:
- Fix commit message(Lucas)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan 
Cc: Licas De Marchi 
Signed-off-by: Matt Roper 
Signed-off-by: Radhakrishna Sripada 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi

[Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

2022-09-28 Thread Radhakrishna Sripada 
From: Matt Roper 

The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)
v4.1:
 - Fix commit message(Lucas)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan 
Cc: Licas De Marchi 
Signed-off-by: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 -
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+   NOP(1),
+   LRI(13, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   NOP(4),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   END
+};
+
 static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+   NOP(1),
+   LRI(15, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   REG(0x120),
+   REG(0x124),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   NOP(2),
+   LRI(2, POSTED),
+   REG16(0x5a8),
+   REG16(0x5ac),
+
+   NOP(6),
+   LRI(1, 0),
+   REG(0x0c8),
+
+   END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
   !intel_engine_has_relative_mmio(engine));
 
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_rcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
else
return gen8_rcs_offsets;
} else {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_xcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
-- 
2.34.1

[Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

2022-09-26 Thread Radhakrishna Sripada 
From: Matt Roper 

The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)
v4.1:
 - Fix commit message(Lucas)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan 
Cc: Licas De Marchi 
Signed-off-by: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 -
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+   NOP(1),
+   LRI(13, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   NOP(4),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   END
+};
+
 static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+   NOP(1),
+   LRI(15, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   REG(0x120),
+   REG(0x124),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   NOP(2),
+   LRI(2, POSTED),
+   REG16(0x5a8),
+   REG16(0x5ac),
+
+   NOP(6),
+   LRI(1, 0),
+   REG(0x0c8),
+
+   END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
   !intel_engine_has_relative_mmio(engine));
 
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_rcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
else
return gen8_rcs_offsets;
} else {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_xcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
-- 
2.34.1

Re: [Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

2022-09-08 Thread Matt Roper 
On Wed, Sep 07, 2022 at 04:33:17PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper 
> 
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re-use the DG2
> context table.
> 
> For render/compute engines, the part of the context images are nearly
> the same, although the layout had a very slight change --- one POSH
> register was removed and the placement of some LRI/noops adjusted
> slightly to compensate.
> 
> v2:
>  - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
>  - Drop unused registers in mtl rcs offsets.(Bala)
>  - Add missing nop in xcs offsets(Bala)
> 
> Bspec: 46261, 46260, 45585
> Cc: Balasubramani Vivekanandan 
> Signed-off-by: Matt Roper 
> Signed-off-by: Radhakrishna Sripada 
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 82 -
>  1 file changed, 80 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 070cec4ff8a4..a2247d39bdb7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
>   END
>  };
>  
> +static const u8 mtl_xcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> + NOP(1),

Shouldn't this be NOP(4)?


Matt

> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + END
> +};
> +
>  static const u8 gen8_rcs_offsets[] = {
>   NOP(1),
>   LRI(14, POSTED),
> @@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = {
>   END
>  };
>  
> +static const u8 mtl_rcs_offsets[] = {
> +   NOP(1),
> +   LRI(13, POSTED),
> +   REG16(0x244),
> +   REG(0x034),
> +   REG(0x030),
> +   REG(0x038),
> +   REG(0x03c),
> +   REG(0x168),
> +   REG(0x140),
> +   REG(0x110),
> +   REG(0x1c0),
> +   REG(0x1c4),
> +   REG(0x1c8),
> +   REG(0x180),
> +   REG16(0x2b4),
> +
> +   NOP(1),
> +   LRI(9, POSTED),
> +   REG16(0x3a8),
> +   REG16(0x28c),
> +   REG16(0x288),
> +   REG16(0x284),
> +   REG16(0x280),
> +   REG16(0x27c),
> +   REG16(0x278),
> +   REG16(0x274),
> +   REG16(0x270),
> +
> +   NOP(2),
> +   LRI(2, POSTED),
> +   REG16(0x5a8),
> +   REG16(0x5ac),
> +
> +   NOP(6),
> +   LRI(1, 0),
> +   REG(0x0c8),
> +
> +   END
> +};
> +
>  #undef END
>  #undef REG16
>  #undef REG
> @@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
> *engine)
>  !intel_engine_has_relative_mmio(engine));
>  
>   if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_rcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>   return dg2_rcs_offsets;
>   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
>   return xehp_rcs_offsets;
> @@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
> *engine)
>   else
>   return gen8_rcs_offsets;
>   } else {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_xcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>   return dg2_xcs_offsets;
>   else if (GRAPHICS_VER(engine->i915) >= 12)
>   return gen12_xcs_offsets;
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

2022-09-07 Thread Radhakrishna Sripada 
From: Matt Roper 

The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Drop unused registers in mtl rcs offsets.(Bala)
 - Add missing nop in xcs offsets(Bala)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan 
Signed-off-by: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 82 -
 1 file changed, 80 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4..a2247d39bdb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+   NOP(1),
+   LRI(13, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   NOP(1),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   END
+};
+
 static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = {
END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+   NOP(1),
+   LRI(13, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   NOP(2),
+   LRI(2, POSTED),
+   REG16(0x5a8),
+   REG16(0x5ac),
+
+   NOP(6),
+   LRI(1, 0),
+   REG(0x0c8),
+
+   END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
   !intel_engine_has_relative_mmio(engine));
 
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_rcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
else
return gen8_rcs_offsets;
} else {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_xcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
-- 
2.34.1