[Intel-gfx] [PATCH v5 1/4] drm/i915: Reserve some kernel space per vm

[Andrzej Hajda]

Reserve one page in each vm for kernel space to use for things
such as workarounds.

v2: use real memory, do not decrease vm.total
v4: reserve only one page and explain flag
v5: remove allocated object on ppgtt cleanup

Suggested-by: Chris Wilson <chris.p.wil...@linux.intel.com>
Signed-off-by: Andrzej Hajda <andrzej.ha...@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cav...@intel.com>
Reviewed-by: Nirmoy Das <nirmoy....@intel.com>
Reviewed-by: Andi Shyti <andi.sh...@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 42 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gtt.h  |  4 ++++
 2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9895e18df0435a..90adb4751c4d8a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -5,6 +5,7 @@
 
 #include <linux/log2.h>
 
+#include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_lmem.h"
 
 #include "gen8_ppgtt.h"
@@ -222,6 +223,9 @@ static void gen8_ppgtt_cleanup(struct i915_address_space 
*vm)
 {
        struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 
+       if (vm->rsvd.obj)
+               i915_gem_object_put(vm->rsvd.obj);
+
        if (intel_vgpu_active(vm->i915))
                gen8_ppgtt_notify_vgt(ppgtt, false);
 
@@ -950,6 +954,40 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
        return ERR_PTR(err);
 }
 
+static int gen8_init_rsvd(struct i915_address_space *vm)
+{
+       struct drm_i915_private *i915 = vm->i915;
+       struct drm_i915_gem_object *obj;
+       struct i915_vma *vma;
+       int ret;
+
+       /* The memory will be used only by GPU. */
+       obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
+                                         I915_BO_ALLOC_VOLATILE |
+                                         I915_BO_ALLOC_GPU_ONLY);
+       if (IS_ERR(obj))
+               obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+       if (IS_ERR(obj))
+               return PTR_ERR(obj);
+
+       vma = i915_vma_instance(obj, vm, NULL);
+       if (IS_ERR(vma)) {
+               ret = PTR_ERR(vma);
+               goto unref;
+       }
+
+       ret = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH);
+       if (ret)
+               goto unref;
+
+       vm->rsvd.vma = i915_vma_make_unshrinkable(vma);
+       vm->rsvd.obj = obj;
+       return 0;
+unref:
+       i915_gem_object_put(obj);
+       return ret;
+}
+
 /*
  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
  * with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1031,6 +1069,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
        if (intel_vgpu_active(gt->i915))
                gen8_ppgtt_notify_vgt(ppgtt, true);
 
+       err = gen8_init_rsvd(&ppgtt->vm);
+       if (err)
+               goto err_put;
+
        return ppgtt;
 
 err_put:
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index b471edac269920..028a5a988eea02 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -249,6 +249,10 @@ struct i915_address_space {
        struct work_struct release_work;
 
        struct drm_mm mm;
+       struct {
+               struct drm_i915_gem_object *obj;
+               struct i915_vma *vma;
+       } rsvd;
        struct intel_gt *gt;
        struct drm_i915_private *i915;
        struct device *dma;

-- 
2.34.1