[Intel-gfx] [PATCH v5 12/22] drm/i915/mtl: C20 HDMI state calculations

[Mika Kahola]

Add C20 HDMI state calculations and put HDMI table definitions
in use.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 23ebea25aaa9..55ec256c0379 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1632,6 +1632,8 @@ intel_c20_pll_tables_get(struct intel_crtc_state 
*crtc_state,
 {
        if (intel_crtc_has_dp_encoder(crtc_state)) {
                return mtl_c20_dp_tables;
+       } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+               return mtl_c20_hdmi_tables;
        }
 
        MISSING_CASE(encoder->type);
@@ -1672,9 +1674,19 @@ static int intel_c10mpllb_calc_state(struct 
intel_crtc_state *crtc_state,
 static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
                                   struct intel_encoder *encoder)
 {
+       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+       enum phy phy = intel_port_to_phy(i915, encoder->port);
        const struct intel_c20pll_state * const *tables;
        int i;
 
+       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+               if (intel_c20_phy_check_hdmi_link_rate(crtc_state->port_clock) 
!= MODE_OK) {
+                       drm_dbg_kms(&i915->drm, "Can't support HDMI link rate 
%d on phy %c.\n",
+                                   crtc_state->port_clock, phy_name(phy));
+                       return -EINVAL;
+               }
+       }
+
        tables = intel_c20_pll_tables_get(crtc_state, encoder);
        if (!tables)
                return -EINVAL;
-- 
2.34.1