Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.

v2: Use the existing intel_get_pipe_timings and do the dsi
    specific adjustments in the encoder get_config hook.(Ville, Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9d962ea..dbb2712 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1193,6 +1193,34 @@ static void gen11_dsi_disable(struct intel_encoder 
*encoder,
        gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_get_timings(struct intel_encoder *encoder,
+                                 struct intel_crtc_state *pipe_config)
+{
+       struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+       struct drm_display_mode *adjusted_mode =
+                                       &pipe_config->base.adjusted_mode;
+
+       if (intel_dsi->dual_link) {
+               adjusted_mode->crtc_hdisplay *= 2;
+               if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+                       adjusted_mode->crtc_hdisplay -=
+                                               intel_dsi->pixel_overlap;
+               adjusted_mode->crtc_htotal *= 2;
+       }
+       adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
+       adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
+
+       if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+               if (intel_dsi->dual_link) {
+                       adjusted_mode->crtc_hsync_start *= 2;
+                       adjusted_mode->crtc_hsync_end *= 2;
+               }
+       }
+       adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
+       adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
+
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
                                 struct intel_crtc_state *pipe_config)
 {
@@ -1203,6 +1231,7 @@ static void gen11_dsi_get_config(struct intel_encoder 
*encoder,
        pipe_config->port_clock =
                cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
        pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+       gen11_dsi_get_timings(encoder, pipe_config);
        pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 }
 
-- 
1.9.1

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