From: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename the
function accordingly.
Cc: Mika Kahola <mika.kah...@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
Reviewed-by: Mika Kahola <mika.kah...@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index ad76db6c6ab7..1042f1c7b410 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3494,7 +3494,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct
drm_i915_private *i915,
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
before
* update the request state of all DBUS slices.
*/
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void update_mbus(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3553,7 +3553,7 @@ void intel_dbuf_pre_plane_update(struct
intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- update_mbus_pre_enable(state);
+ update_mbus(state);
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
@@ -3575,6 +3575,9 @@ void intel_dbuf_post_plane_update(struct
intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ if (DISPLAY_VER(i915) >= 20)
+ update_mbus(state);
+
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
--
2.34.1
