[Intel-gfx] [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965

2010-07-05 Thread Chris Wilson
The original i965 requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment is required. (So long as we do not start performing asynchronous flips.) Note the

Re: [Intel-gfx] [Mesa-dev] [Mesa3d-dev] mesa doesn't work with compiz (i965 + tips of all branches)

2010-07-05 Thread Maxim Levitsky
2010/7/5 Michel Dänzer mic...@daenzer.net: On Don, 2010-07-01 at 10:32 -0700, Ian Romanick wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Note: I'm sending this reply to mesa-...@lists.freedesktop.org instead of the old mailing list. Maxim Levitsky wrote: On Tue, 2010-06-29 at

Re: [Intel-gfx] [Mesa-dev] [Mesa3d-dev] mesa doesn't work with compiz (i965 + tips of all branches)

2010-07-05 Thread Maxim Levitsky
On Mon, 2010-07-05 at 13:08 +0300, Maxim Levitsky wrote: 2010/7/5 Michel Dänzer mic...@daenzer.net: On Don, 2010-07-01 at 10:32 -0700, Ian Romanick wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Note: I'm sending this reply to mesa-...@lists.freedesktop.org instead of the old

Re: [Intel-gfx] [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965

2010-07-05 Thread Eric Anholt
On Mon, 5 Jul 2010 10:25:57 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: The original i965 requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment

Re: [Intel-gfx] [PATCH] drm/i915: Use 128k alignment for untiled display surface on i965

2010-07-05 Thread Jesse Barnes
On Mon, 5 Jul 2010 10:25:57 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: The original i965 requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment

Re: [Intel-gfx] [PATCH 2/2] drm/i915: remove duplicate PIPE*STAT bit definitions

2010-07-05 Thread Eric Anholt
On Wed, 30 Jun 2010 13:16:00 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: Having two sets has made me think I caught a bug more than once now. Applied this series to -next. pgpD7e5eD06If.pgp Description: PGP signature ___ Intel-gfx mailing

[Intel-gfx] [PATCH 1/2] drm/i915: Use 128k alignment for untiled display surface on i965 (v2)

2010-07-05 Thread Chris Wilson
The original i965, including the revised G35 and Q35, requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment is required. (So long as we do not start

[Intel-gfx] [PATCH 2/2] drm/i915: Include any alternate names by which the device is known.

2010-07-05 Thread Chris Wilson
When trying to keep track of features between the kernel, the 2D driver, mesa and the specs, it helps to list any other name by which the device is referred to. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 52 +++---

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Include any alternate names by which the device is known.

2010-07-05 Thread Chris Wilson
On Mon, 5 Jul 2010 18:01:47 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: When trying to keep track of features between the kernel, the 2D driver, mesa and the specs, it helps to list any other name by which the device is referred to. In adding this list it became apparent that the 2D