On Wed, Jul 10, 2013 at 05:16:54PM -0700, Chad Versace wrote:
On 07/09/2013 07:58 PM, Ben Widawsky wrote:
The algorithm/information was originally written by Chad, though I
changed the control flow, and I think his original code had a couple of
bugs, though I didn't look very hard before
On Thu, Jul 11, 2013 at 12:23 AM, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, Jul 10, 2013 at 07:05:52PM +0200, Daniel Vetter wrote:
On Wed, Jul 10, 2013 at 09:37:10AM -0700, Ben Widawsky wrote:
On Tue, Jul 09, 2013 at 09:15:01AM +0200, Daniel Vetter wrote:
On Mon, Jul 08, 2013 at
Hi everybody!
During booting a pipe state doesn't match error occures.
Reproducibility: high (3 of 3 test boots)
Hardware: Aopen i915GMm-hfs, Pentium-M, opensuse 12.3,
kernel 3.10.0+, git 496322bc91e35007ed754184dcd447a02b6dd685
trace attached.
cu,
Knut
[2.273091] Linux agpgart interface
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On Wed, Jul 10, 2013 at 10:48 PM, Paulo Zanoni przan...@gmail.com wrote:
Which means we're now initializing GEN6_PM* code on SNB, which seems
good. You might want to dedicate a paragraph for this on the commit
message.
On the IRQ patches I wrote (but did not sent yet) I unified the
ILK/SNB
On Wed, Jul 10, 2013 at 06:12:13PM -0300, Paulo Zanoni wrote:
2013/7/4 Daniel Vetter daniel.vet...@ffwll.ch:
This just unifies the vlv code with the snb-hsw code which matched
exactly before the VECS enabling.
So now the VLV code is behaving differently. Is that intentional? You
could
On Thu, Jul 11, 2013 at 8:11 AM, Knut Petersen
knut_peter...@t-online.de wrote:
Hi everybody!
During booting a pipe state doesn't match error occures.
Reproducibility: high (3 of 3 test boots)
Hardware: Aopen i915GMm-hfs, Pentium-M, opensuse 12.3,
kernel 3.10.0+, git
Hi everybody!
During resume from S3 there is a pipe state problem
Reproducibility: high (3 of 3 test resumes)
Hardware: Aopen i915GMm-hfs, Pentium-M, opensuse 12.3,
kernel 3.10.0+, git 496322bc91e35007ed754184dcd447a02b6dd685
Three slightly differing trace attached.
cu,
Knut
[
display.crtc_mode_set will increase pll-refcount, but no one will
decrease pll-refcount when freeze gpu. So when gpu resume from freeze,
pll-refcount is still larger than zero. This is abnormal
Without this patch, connecting vga screen on Haswell platform, there
are following results:
1. when
On Mon, 2013-07-08 at 23:08 -0700, Ben Widawsky wrote:
The GTT and PPGTT can be thought of more generally as GPU address
spaces. Many of their actions (insert entries), state (LRU lists) and
many of their characteristics (size), can be shared. Do that.
The change itself doesn't actually
On Mon, 2013-07-08 at 23:08 -0700, Ben Widawsky wrote:
Formerly: drm/i915: Create VMAs (part 1)
In a previous patch, the notion of a VM was introduced. A VMA describes
an area of part of the VM address space. A VMA is similar to the concept
in the linux mm. However, instead of representing
It's in the PFIT_CONTROL register, but very much associated with the
lvds encoder. So move the readout for it (in the case of an otherwise
disabled pfit) from the pipe to the lvds encoder's get_config
function.
Otherwise we get a pipe state mismatch if we use pipe B for a non-lvds
output and
It's in the PFIT_CONTROL register, but very much associated with the
lvds encoder. So move the readout for it (in the case of an otherwise
disabled pfit) from the pipe to the lvds encoder's get_config
function.
Otherwise we get a pipe state mismatch if we use pipe B for a non-lvds
output and
On Thu, Jul 11, 2013 at 01:35:40PM +0200, Daniel Vetter wrote:
It's in the PFIT_CONTROL register, but very much associated with the
lvds encoder. So move the readout for it (in the case of an otherwise
disabled pfit) from the pipe to the lvds encoder's get_config
function.
Otherwise we get
Hi Knut,
When you test this patch please grab a dmesg with drm.debug=0xe
regardless of outcome, I'd like to check a few other odd things with
your system (which seem to not be directly related to the issue at
hand).
Thanks, Daniel
On Thu, Jul 11, 2013 at 1:35 PM, Daniel Vetter
Cc lists this time around ...
-Daniel
On Thu, Jul 11, 2013 at 2:06 PM, Daniel Vetter dan...@ffwll.ch wrote:
Hi Dave,
One feature latecomer, I've forgotten to merge the patch to reeanble the
Haswell power well feature now that the audio interaction is fixed up.
Since that was the only unfixed
On Thu, Jul 04, 2013 at 11:35:30PM +0200, Daniel Vetter wrote:
The code to handle it is broken - there's simply no code to clear CS
parser errors on gen5+. And behold, for all the other rings we also
don't enable it!
Leave the handling code itself in place just to be consistent with the
On Thu, 2013-06-06 at 10:22 +0200, Daniel Vetter wrote:
No need to call the -pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.
v2: Rebase on top of the newly-colored BUG_ONs.
Cc: Jani Nikula jani.nik...@intel.com
Signed-off-by:
On Thu, 11 Jul 2013 16:02:27 +0800
Xiong Zhang xiong.y.zh...@intel.com wrote:
display.crtc_mode_set will increase pll-refcount, but no one will
decrease pll-refcount when freeze gpu. So when gpu resume from freeze,
pll-refcount is still larger than zero. This is abnormal
Without this patch,
Requested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
tests/Makefile.am | 1 +
tests/drm_lib.sh | 4
tests/tools_test | 20
3 files changed, 25 insertions(+)
create mode 100755 tests/tools_test
diff --git
On Thu, Jul 11, 2013 at 06:29:15PM +0200, Knut Petersen wrote:
On 11.07.2013 13:49, Chris Wilson wrote:
On Thu, Jul 11, 2013 at 01:35:40PM +0200, Daniel Vetter wrote:
It's in the PFIT_CONTROL register, but very much associated with the
lvds encoder. So move the readout for it (in the case of
On Thu, Jul 11, 2013 at 6:53 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Thu, 11 Jul 2013 16:02:27 +0800
Xiong Zhang xiong.y.zh...@intel.com wrote:
display.crtc_mode_set will increase pll-refcount, but no one will
decrease pll-refcount when freeze gpu. So when gpu resume from freeze,
On Thu, Jul 11, 2013 at 09:59:46AM -0700, Ben Widawsky wrote:
Requested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
tests/Makefile.am | 1 +
tests/drm_lib.sh | 4
tests/tools_test | 20
3 files changed, 25
On Mon, Jul 8, 2013 at 7:25 PM, Rodrigo Vivi rodrigo.v...@gmail.com wrote:
On Fri, Jul 5, 2013 at 5:32 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jul 01, 2013 at 05:47:39PM -0300, Rodrigo Vivi wrote:
Again, Thank you very much for your comments.
Replying what I did and why I didn't here
somewhere before commit 496322b (yesterday's kernel) resolution
switching on my laptop broke. The screen switches to the right
resolution but the screen is not horizontally centered. The screen is
aligned left and the last vertical line is repeated until the right side
of the screen. Normally
On Thu, Jul 11, 2013 at 8:04 PM, Hans de Bruin jmdebr...@xmsnet.nl wrote:
somewhere before commit 496322b (yesterday's kernel) resolution switching on
my laptop broke. The screen switches to the right resolution but the screen
is not horizontally centered. The screen is aligned left and the
On Thu, Jun 20, 2013 at 08:01:47AM +0800, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
The dereference should be moved below the NULL test.
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
drivers/gpu/drm/i915/i915_gem_context.c | 3 ++-
1 file changed,
Right now code checkers point out that we try to dereference file before
testing it for NULL.
This check doesn't seem necessary as file needs to be valid for the
ioctl() code to run.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 3 ---
1
If intel_sdvo_get_value() fails here, val is unitialized and the cross
check won't check anything.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_sdvo.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
The algorithm/information was originally written by Chad, though I
changed the control flow, and I think his original code had a couple of
bugs, though I didn't look very hard before rewriting. That could have
also been different interpretations of the spec.
I've tested this on two platforms, and
v2: Use the new param
CC: Chad Versace chad.vers...@linux.intel.com
CC: Bryan Bell bryan.j.b...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
tools/Makefile.am | 1 +
tools/intel_get_llc_size.c | 58 ++
2 files changed, 59
v2: Remove the reg write test because it breaks pre gen5
Add the llc size param test
Requested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
tests/Makefile.am | 1 +
tests/drm_lib.sh | 4
tests/tools_test | 21 +
3 files
Came accross two open coding of for_each_pipe(), might as well use the
macro.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
On Thu, Jul 11, 2013 at 09:05:45PM +0200, Hans de Bruin wrote:
On 07/11/2013 08:22 PM, Daniel Vetter wrote:
On Thu, Jul 11, 2013 at 8:04 PM, Hans de Bruin jmdebr...@xmsnet.nl wrote:
somewhere before commit 496322b (yesterday's kernel) resolution switching on
my laptop broke. The screen
I don't see mei_me_pci_suspend() calling mei_disable_interrupts() and
pci_disable_msi().
Suspend calls mei_reset with request for disabling interrupts
I'm pretty sure I do free_irq and I do disable_msi in the suspend (Hope we are
looking at the same code)
I don't see a call to
On Thu, Jul 11, 2013 at 07:46:00PM +0100, Damien Lespiau wrote:
If intel_sdvo_get_value() fails here, val is unitialized and the cross
check won't check anything.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_sdvo.c | 5 -
1 file changed, 4
On Thu, Jul 11, 2013 at 08:10:54PM +0100, Damien Lespiau wrote:
Came accross two open coding of for_each_pipe(), might as well use the
macro.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Queued for -next, thanks for the patch.
-Daniel
---
drivers/gpu/drm/i915/intel_display.c | 4
No need to call the -pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.
v2: Rebase on top of the newly-colored BUG_ONs.
v3: Reinstate the lost write of the DPLL_MD register, spotted by Imre.
Cc: Imre Deak imre.d...@intel.com
Cc: Jani Nikula
On Thu, Jul 11, 2013 at 09:52:33PM +0200, Daniel Vetter wrote:
On Thu, Jul 11, 2013 at 07:46:00PM +0100, Damien Lespiau wrote:
If intel_sdvo_get_value() fails here, val is unitialized and the cross
check won't check anything.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
On Thu, Jul 11, 2013 at 11:52:12AM -0700, Ben Widawsky wrote:
The algorithm/information was originally written by Chad, though I
changed the control flow, and I think his original code had a couple of
bugs, though I didn't look very hard before rewriting. That could have
also been different
On Thu, Jul 11, 2013 at 07:31:34PM +0100, Damien Lespiau wrote:
Right now code checkers point out that we try to dereference file before
testing it for NULL.
This check doesn't seem necessary as file needs to be valid for the
ioctl() code to run.
This whole function was a copy'n'paste
On 07/11/2013 09:41 PM, Daniel Vetter wrote:
On Thu, Jul 11, 2013 at 09:05:45PM +0200, Hans de Bruin wrote:
On 07/11/2013 08:22 PM, Daniel Vetter wrote:
On Thu, Jul 11, 2013 at 8:04 PM, Hans de Bruin jmdebr...@xmsnet.nl wrote:
somewhere before commit 496322b (yesterday's kernel) resolution
I'm resending full series again because after accepting most of suggestions
and rebasing again on drm-intel-nightly most of patches got some kind of
conflict so the full series is here again.
First 3 patches on this series are already reviewed and I'd be glad if they
were merged asap to avoid
From: Shobhit Kumar shobhit.ku...@intel.com
SDP header and SDP VSC header as per eDP 1.3 spec, section 3.5,
chapter PSR Secondary Data Package Support.
v2: Modified and corrected the structures to be more in line for
kernel coding guidelines and rebased the code on Paulo's DP patchset
v3:
From: Shobhit Kumar shobhit.ku...@intel.com
v2: reuse of just created is_edp_psr and put it at right place.
v3: move is_edp_psr above intel_edp_disable
v4: remove parentheses. Noticed by Paulo.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
Prep patch for reuse aux_clock_divider with EDP_PSR_AUX_CTL setup.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 58 +++--
1 file changed, 33 insertions(+), 25
Adding Enable and Disable PSR functionalities. This includes setting the
PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
enabling PSR in the sink via DPCD register and finally enabling PSR on
the host.
This patch is based on initial PSR code by Sateesh Kavuri and Kumar
v2: Prefer seq_puts to seq_printf by Paulo Zanoni.
v3: small changes like avoiding calling dp_to_dig_port twice as noticed by
Paulo Zanoni.
v4: Avoiding reading non-existent registers - noticed by Paulo
on first psr debugfs patch.
v5: Accepting more suggestions from Paulo:
* check sw
Adding support for PSR Status, PSR entry counter and performance counters.
Heavily based on initial work from Shobhit.
v2: Fix PSR Status Link bits by Paulo Zanoni.
v3: Prefer seq_puts to seq_printf by Paulo Zanoni.
v4: Fix identation by Paulo Zanoni.
v5: Return earlier if it isn't Haswell in
v2: prefer seq_puts to seq_printf detected by Paulo Zanoni.
v3: PSR is disabled by default. Without userspace ready it
will cause regression for kde and xdm users
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
Required function to disable PSR when going to console mode.
But also can be used whenever PSR mode entry conditions changed.
v2: Add it before PSR Hook. Update function not really been called yet.
v3: Fix coding style detected by checkpatch by Paulo Zanoni.
v4: do_enable must be static as Paulo
PSR tracking engine in HSW doesn't detect automagically some directly copy area
operations through scanout so we will have to kick it manually and
reschedule it to come back to normal operation as soon as possible.
v2: Before PSR Hook. Don't force it when busy yet.
v3/v4: Solved small conflict.
This global value allows userspace know when PSR is enabled.
This will allow userspace emit more busy_ioctl when doing directly copy_area
operations through scanout allowing forced psr exit.
v2: Check for PSR enabled instead of active. (by Chris Wilson)
v3: Use existing intel_edp_is_psr_enabled
PSR must be enabled after transcoder and port are running.
And it is only available for HSW.
v2: move enable/disable to intel_ddi
v3: The spec suggests PSR should be disabled even before backlight (by pzanoni)
v4: also disabling and enabling whenever panel is disabled/enabled.
v5: make it last
It's currently unused upstream, and just gets in the way internally. If
things are really hosed for some reason on a given platform, users can
still pass a bogus param to i915 to disable it (e.g. for installers with
half baked hw support). But really, if that happens in practice, we've
failed
On Thu, Jul 11, 2013 at 02:14:06PM +0300, Imre Deak wrote:
On Mon, 2013-07-08 at 23:08 -0700, Ben Widawsky wrote:
The GTT and PPGTT can be thought of more generally as GPU address
spaces. Many of their actions (insert entries), state (LRU lists) and
many of their characteristics (size), can
On Thu, Jul 11, 2013 at 02:20:50PM +0300, Imre Deak wrote:
On Mon, 2013-07-08 at 23:08 -0700, Ben Widawsky wrote:
Formerly: drm/i915: Create VMAs (part 1)
In a previous patch, the notion of a VM was introduced. A VMA describes
an area of part of the VM address space. A VMA is similar to
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