From: Deepak S deepa...@linux.intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period
At Wed, 26 Mar 2014 20:10:09 +0100,
Daniel Vetter wrote:
It apparently blows up on some machines. This functionally reverts
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Wed Oct 16 09:21:30 2013 -0700
drm/i915: Disable GGTT
On Thu, Mar 27, 2014 at 7:41 AM, Takashi Iwai ti...@suse.de wrote:
It apparently blows up on some machines. This functionally reverts
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Wed Oct 16 09:21:30 2013 -0700
drm/i915: Disable
At Thu, 27 Mar 2014 07:55:57 +0100,
Daniel Vetter wrote:
On Thu, Mar 27, 2014 at 7:41 AM, Takashi Iwai ti...@suse.de wrote:
It apparently blows up on some machines. This functionally reverts
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky benjamin.widaw...@intel.com
On Wed, Mar 26, 2014 at 05:09:53PM -0700, Ben Widawsky wrote:
On Fri, Mar 21, 2014 at 12:41:53PM +, Chris Wilson wrote:
As Broadwell has an increased virtual address size, it requires more
than 32 bits to store offsets into its address space. This includes the
debug registers to track
On Wed, Mar 26, 2014 at 05:09:53PM -0700, Ben Widawsky wrote:
On Fri, Mar 21, 2014 at 12:41:53PM +, Chris Wilson wrote:
+#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
+ u32 upper = I915_READ(upper_reg); \
+ u32 lower =
On Thu, Mar 27, 2014 at 3:19 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Mar 26, 2014 at 10:17:51PM +0100, Daniel Vetter wrote:
Note that the sleep(5); to fully idle the gpu is _really_ important.
Without it the bug is not exhibited.
The issue at hand is that after
Actually cc'ing Deepak might help.
-Daniel
On Thu, Mar 27, 2014 at 8:45 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
On Thu, Mar 27, 2014 at 3:19 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Mar 26, 2014 at 10:17:51PM +0100, Daniel Vetter wrote:
Note that the sleep(5); to
On Thu, Mar 27, 2014 at 08:45:33AM +0100, Daniel Vetter wrote:
On Thu, Mar 27, 2014 at 3:19 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Mar 26, 2014 at 10:17:51PM +0100, Daniel Vetter wrote:
Note that the sleep(5); to fully idle the gpu is _really_ important.
Without it the
On Wed, Mar 26, 2014 at 11:26:05AM -0700, Volkin, Bradley D wrote:
On Wed, Mar 26, 2014 at 10:37:44AM -0700, Kenneth Graunke wrote:
On 03/26/2014 09:38 AM, Daniel Vetter wrote:
On Wed, Mar 26, 2014 at 09:03:58AM -0700, Volkin, Bradley D wrote:
On Tue, Mar 25, 2014 at 11:21:23PM -0700,
The speculation is that we can conserve more power by masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@intel.com
Cc: Ville Syrjälä
This reverts commit 2754436913b94626a5414d82f0996489628c513d.
Conflicts:
drivers/gpu/drm/i915/i915_irq.c
The partial application of interrupt masking without regard to other
pathways for adjusting the RPS frequency results in completely disabling
the PM interrupts. This leads to
On Mar-26-2014 6:19 PM, Jani Nikula wrote:
On Wed, 26 Mar 2014, Jani Nikula jani.nik...@linux.intel.com wrote:
This and the following patches need to be rebased on top of current
-nightly.
On Fri, 07 Mar 2014, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat
On Thu, Mar 27, 2014 at 08:24:21AM +, Chris Wilson wrote:
The speculation is that we can conserve more power by masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc:
The speculation is that we can conserve more power by masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@intel.com
Cc: Ville Syrjälä
On Thu, Mar 27, 2014 at 08:35:11AM +, Chris Wilson wrote:
The speculation is that we can conserve more power by masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).
Drat, cut'n'paste comment doesn't completely apply to vlv.
On Mar-26-2014 6:25 PM, Jani Nikula wrote:
On Fri, 07 Mar 2014, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
From: Sagar Kamble sagar.a.kam...@intel.com
v2: Added description for src-color and constant-alpha property.
[Review by Laurent Pinchart]
v3: Fixed typos. [Review by David Hermann]
Cc: Rob Landley rob at landley.net
Cc: Dave Airlie airlied at redhat.com
Cc: Daniel Vetter daniel.vetter at
When trying to determine whether RPS is working as intended, more
information is better. In particular, what interrupts are being
generated and the various thresholds for generating them.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_debugfs.c | 16
From: Ville Syrjälä ville.syrj...@linux.intel.com
In commit
commit 6375b768a9850b6154478993e5fb566fa4614a9c
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Mon Mar 3 11:33:36 2014 +0200
drm/i915: Reject 165MHz modes w/ DVI monitors
the driver started to filter out display
On Mar-26-2014 6:06 PM, Jani Nikula wrote:
On Fri, 07 Mar 2014, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The
From: Sagar Kamble sagar.a.kam...@intel.com
v2: Added description for src-color and constant-alpha property.
[Review by Laurent Pinchart]
v3: Fixed typos. [Review by David Herrmann]
Cc: Rob Landley rob at landley.net
Cc: Dave Airlie airlied at redhat.com
Cc: Daniel Vetter daniel.vetter at
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Looks like there are some redundant lines in the main loop of
i915_gem_object_get_pages_gtt.
v2: Put CONFIG_SWIOTLB back in.
I haven't tested this so just RFC please. Not sure that
seven lines net less is worth this. It just made it clerer
to a
On Mar-26-2014 6:35 PM, Jani Nikula wrote:
On Fri, 07 Mar 2014, Vandana Kannan vandana.kan...@intel.com wrote:
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If
On Thu, 27 Mar 2014, Vandana Kannan vandana.kan...@intel.com wrote:
On Mar-26-2014 6:06 PM, Jani Nikula wrote:
On Fri, 07 Mar 2014, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS support and Mode type from VBT fields.
The
On 03/27/2014 10:18 AM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Looks like there are some redundant lines in the main loop of
i915_gem_object_get_pages_gtt.
v2: Put CONFIG_SWIOTLB back in.
I haven't tested this so just RFC please. Not sure that
seven lines net
On Thu, Mar 27, 2014 at 09:37:36AM +, Chris Wilson wrote:
On Thu, Mar 27, 2014 at 11:08:45AM +0200, ville.syrj...@linux.intel.com wrote:
So relax the checks a bit, and apply the single-link DVI dotclock limit
only when filtering the mode list, and ignore the limit when setting
a user
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a visible stutter. Boosting the GPU frequency
doesn't prevent us
Hi
On Thu, Mar 27, 2014 at 10:50 AM, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
v2: Added description for src-color and constant-alpha property.
[Review by Laurent Pinchart]
v3: Fixed typos. [Review by David Herrmann]
Cc: Rob Landley rob at
At Thu, 27 Mar 2014 07:41:41 +0100,
Takashi Iwai wrote:
At Wed, 26 Mar 2014 20:10:09 +0100,
Daniel Vetter wrote:
It apparently blows up on some machines. This functionally reverts
commit 828c79087cec61eaf4c76bb32c222fbe35ac3930
Author: Ben Widawsky benjamin.widaw...@intel.com
2014-03-19 14:50 GMT-03:00 Ben Widawsky b...@bwidawsk.net:
On Wed, Mar 19, 2014 at 09:28:32AM +0100, Daniel Vetter wrote:
On Tue, Mar 18, 2014 at 11:20:09AM -0700, Ben Widawsky wrote:
On Fri, Mar 07, 2014 at 08:10:24PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
On Thu, Mar 27, 2014 at 09:06:14AM +, Chris Wilson wrote:
When trying to determine whether RPS is working as intended, more
information is better. In particular, what interrupts are being
generated and the various thresholds for generating them.
Signed-off-by: Chris Wilson
On Thu, Mar 27, 2014 at 01:03:31PM +0200, Ville Syrjälä wrote:
On Thu, Mar 27, 2014 at 09:37:36AM +, Chris Wilson wrote:
On Thu, Mar 27, 2014 at 11:08:45AM +0200, ville.syrj...@linux.intel.com
wrote:
So relax the checks a bit, and apply the single-link DVI dotclock limit
only when
On Thu, Mar 27, 2014 at 12:01:11PM +, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a
2014-03-18 17:29 GMT-03:00 Ben Widawsky b...@bwidawsk.net:
On Fri, Mar 07, 2014 at 08:10:30PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
On the preinstall stage we should just disable all the interrupts, but
we currently enable all the south display interrupts due
2014-03-18 17:43 GMT-03:00 Ben Widawsky b...@bwidawsk.net:
On Fri, Mar 07, 2014 at 08:10:34PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
So we can merge all the common code from postinstall and uninstall.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote:
The speculation is that we can conserve more power by masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S
On Thursday 27 March 2014 02:36 PM, Chris Wilson wrote:
When trying to determine whether RPS is working as intended, more
information is better. In particular, what interrupts are being
generated and the various thresholds for generating them.
Signed-off-by: Chris Wilson
On Thu, Mar 27, 2014 at 08:21:29PM +0530, Deepak S wrote:
On VLV, gen6_enable_rps_interrupts is used to enable turbo interrutpts.
I think we need to extend gen6_rps_pm_mask to valleyview also?
Check patch 4/3.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
From: Siluvery, Arun arun.siluv...@intel.com
This patch series adds a new ioctl to resize a gem object.
This is required in cases where the actual size of the object is not known
at the time of creation and there is chance that we may need more space later.
A typical use case is memory
From: Siluvery, Arun arun.siluv...@intel.com
Add new case to test gem object resize implementation.
The current test creates two objects, one of them is resizeable.
Before resize it is filled with data from source object using GPU blt.
Object is resized and then filled the new space with
From: Siluvery, Arun arun.siluv...@intel.com
This patch adds a new ioctl to resize gem object. If the object is created
as resizeable scatter/gather table contains dummy entries that point to a
scratch page. A marker denotes end of real pages.
This ioctl creates new pages and updates the dummy
From: Siluvery, Arun arun.siluv...@intel.com
GEM object size is fixed and it is tightly coupled in i915.
To make it resizeable a lazy allocation approach is used.
Out of the total size of object, backing store is allocated partially.
The scatter/gather entries for the remaining pages point to
From: Siluvery, Arun arun.siluv...@intel.com
This patch adds data structure to handle gem object resize.
One such usecase where it is required is mipmaps; you cannot know
whether higher level mipmaps are required at the time of creating them,
so it is best to defer memory allocation for higher
These are dependency patches for enabling RPM on VLV. I'm sending them
in advance because they could be applied independently and the second
one might fix some eDP issues.
Imre Deak (2):
drm/i915: vlv: cache current CD clock rate
drm/i915: vlv: get power domain for eDP vdd
Instead of reading out the CD clock rate from the HW at each modeset, do
this only during driver init and resume and use the cached value during
modeset. This moves things towards a state where the sw and hw side
setup is separated. It's also needed for VLV RPM, where we don't put
device into D0
Besides D0 device state we need the proper power wells to be on on
some platforms, so get the port power domain reference instead of an RPM
reference.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 20 +---
1 file changed, 17 insertions(+), 3
[snip]
On Thu, Mar 27, 2014 at 12:57:21AM -0700, Daniel Vetter wrote:
Another one that blows is igt/gen7_forcewake_mt. Not sure yet whether it's
an issue with the test or the checker:
https://bugs.freedesktop.org/show_bug.cgi?id=76670
For this one, the parser rejects an
From: Oscar Mateo oscar.ma...@intel.com
Now that our global default contexts are correctly created and we have
finished the refactoring, it's time to allow other kind of contexts.
As we said earlier, logical ring contexts created by the user have their
own ringbuffer: not only the backing pages,
From: Ben Widawsky benjamin.widaw...@intel.com
A context switch occurs by submitting a context descriptor to the
ExecList Submission Port. Given that we can now initialize a context,
it's possible to begin implementing the context switch by creating the
descriptor and submitting it to ELSP
From: Oscar Mateo oscar.ma...@intel.com
From here on, we define a stand-alone context as the first context with
a given ID to be created for a new fd or a new context create ioctl. This
is the one we can easily find using integer ID management. On the other
hand, dependent contexts are
From: Oscar Mateo oscar.ma...@intel.com
Since we cannot tell apart which specific context the user refers too,
get stats from all the per-engine cotexts with the same ID.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 15 +++
1 file
From: Oscar Mateo oscar.ma...@intel.com
Finally, start queueing request on write_tail. Also, remove remaining
legacy context switches.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c| 9 ++---
drivers/gpu/drm/i915/i915_gem_context.c| 10
From: Oscar Mateo oscar.ma...@intel.com
Explain i915_lrc.c with some execlists notes
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
v2: Add notes on logical ring context creation.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_lrc.c | 78
From: Oscar Mateo oscar.ma...@intel.com
Even though we have one Hardware Status Page per context, we are still
managing the seqnos per engine. Therefore, the sequence number must be
written to a consistent place for all contexts: one of the global
default contexts.
Signed-off-by: Thomas Daniel
From: Ben Widawsky benjamin.widaw...@intel.com
Semaphores have changed, so let's not submit useless commands to the
ring.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
v2: Several rebases.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 23
From: Ben Widawsky benjamin.widaw...@intel.com
There are a few big differences between context init and fini with the
previous implementation of hardware contexts. One of them is
demonstrated in this patch: we must do a context initialization for
every ring.
The patch will still fail at context
From: Ben Widawsky benjamin.widaw...@intel.com
With our setup in previous patches, we've allocated one default context
per ring. Now, each of those contexts holds a pointer to the default
ringbuffers and makes its own allocation of the backing objects.
To reiterate the TODO in the patch: the
From: Ben Widawsky benjamin.widaw...@intel.com
The status page with logical ring contexts is included already in the
context object. Update the init and cleanup functions to reflect that. The
status page is offset 0 from the context object when using logical ring
contexts.
Signed-off-by: Ben
From: Ben Widawsky benjamin.widaw...@intel.com
For the most part, logical rinf context objects are similar to hardware
contexts in that the backing object is meant to be opaque. There are
some exceptions where we need to poke certain offsets of the object for
initialization, updating the tail
From: Oscar Mateo oscar.ma...@intel.com
For the moment, this is simple and works allright. When we start
having a lot of contexts, this is going to become problematic.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_lrc.c | 21 +++--
1 file
From: Oscar Mateo oscar.ma...@intel.com
Since the ringbuffer can live in the ring (pre-GEN8) or in the context (GEN8+)
we need functions that are aware of this. After this commit and some of the
previous, this new ringbuffer functions finally are:
intel_ringbuffer_get
intel_ringbuffer_begin
From: Thomas Daniel thomas.dan...@intel.com
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on
From: Oscar Mateo oscar.ma...@intel.com
On execbuffer, either...:
A) there is not standalone context (and we error: user provided ctx id is
invalid).
B) the standalone context is the one we are looking for (and we return it).
C) the standalone context is blank (and we populate and return it).
From: Oscar Mateo oscar.ma...@intel.com
Users can create contexts either implicitly by opening an fd, or
explicitly by the context create ioctl. In either case, this context
needs to be corectly populated with advanced stuff. For the moment
we consider all the user contexts to be of the render
From: Oscar Mateo oscar.ma...@intel.com
This commit changes the ABI, so it is provided separately so that it can be
dropped by the maintainer is so he wishes.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_lrc.c | 6 --
1 file changed, 6 deletions(-)
diff
From: Oscar Mateo oscar.ma...@intel.com
As a separate function, we can decide wether we want a context with real
information about which engine it uses, or a blank context for which to
make a deferred decision.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_lrc.c
From: Oscar Mateo oscar.ma...@intel.com
We need it (at least) to properly update the last retired head.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
From: Oscar Mateo oscar.ma...@intel.com
Plumb ring-write_tail with a context argument, which in turn
means plumbing ring-add_request, which in turn, etc The
idea is that, by the time we would usually update the tail
register, we know which context we are working with and,
therefore, we can
From: Oscar Mateo oscar.ma...@intel.com
Hi all,
This patch series implement execlists for GEN8+. Before continuing, it is
important to mention that I might have taken upon myself to assemble the series
and rewrite it for upstreaming, but many people have worked on this series
before me.
From: Ben Widawsky benjamin.widaw...@intel.com
This modifies the init code to try to start logical ring contexts when
possible, and fall back to legacy ringbuffers when not.
Most importantly, things make things easy if we do the context creation
before ringbuffer initialization. Upcoming patches
From: Ben Widawsky benjamin.widaw...@intel.com
It's beneficial to be able to get a name, base, and id before we've
actually initialized the rings. This ability was effectively destroyed
in the ringbuffer fire which Daniel started.
With the simple early init function, that ability is restored.
From: Oscar Mateo oscar.ma...@intel.com
We are going to reuse it during logical ring context creation.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
2 files changed, 3 insertions(+), 1
From: Ben Widawsky benjamin.widaw...@intel.com
for_each_ring() iterates over all rings supported by the hardware, not
just those which have been initialized as in for_each_active_ring()
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Acked-by: Oscar Mateo oscar.ma...@intel.com
---
From: Oscar Mateo oscar.ma...@intel.com
The write tail function is a very special place for execlists: since
all access to the ring is mediated through requests (thanks to
Chris Wilson's Write RING_TAIL once per-request for that) and all
requests end up with a write tail, this is the place we are
From: Oscar Mateo oscar.ma...@intel.com
Continue the refactoring: do not init or clean a ringbuffer when you
actually mean a ring.
Again, no functional changes.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 6 +++---
From: Oscar Mateo oscar.ma...@intel.com
This patch should have no functional changes.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 37 +++--
1 file changed, 12 insertions(+), 25 deletions(-)
diff --git
From: Oscar Mateo oscar.ma...@intel.com
Following the logic behind the previous patch, the ringbuffers and the rings
belong in different structs. We keep the relationship between the two via the
default_ringbuf living inside each ring/engine.
This commit should not introduce functional changes
From: Oscar Mateo oscar.ma...@intel.com
Consisting on 12 bits with the filepriv ID, 5 bits with the context
ID and 3 bits with the ring ID.
Note: this changes the ABI (only 4096 file descriptors are now allowed,
with 8 contexts per-fd) and will break some IGT tests (those that open
a big number
From: Oscar Mateo oscar.ma...@intel.com
Since context IDs are not globally unique anymore (they are only unique
for a given file descriptor), we can use the new file_priv ID in
combination with the context ID to unequivocally refer to a context.
The ID 0 remains to be used internally by i915
From: Thomas Daniel thomas.dan...@intel.com
BSPEC says: SW must set Force Wakeup bit to prevent GT from
entering C6 while ELSP writes are in progress.
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
Acked-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
From: Thomas Daniel thomas.dan...@intel.com
We need to attend context switch interrupts from all rings. Also, fixed writing
IMR/IER and added HWSTAM at ring init time.
Notice that, if added to irq_enable_mask, the context switch interrupts would
be incorrectly masked out when the user interrupts
From: Oscar Mateo oscar.ma...@intel.com
Each logical ring context has the PDPs in the context object, so update
them before submission. This should work both for Aliasing PPGTT
(nothing will be changed) and Full PPGTT.
Also, don't write PDP in the legacy way when using logical ring contexts
From: Ben Widawsky benjamin.widaw...@intel.com
Logical ring contexts do not need most of the ring init: we just need
the pipe control object for the render ring and a few other things
(some of which will be added later).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
I already got a review from Brad Volkin on this that I agree with: change the
write_tail vfunc name to something different, like submit. If no one
disagrees, I´ll change it in the next submission.
-Original Message-
From: Mateo Lozano, Oscar
Sent: Thursday, March 27, 2014 6:00 PM
From: Oscar Mateo oscar.ma...@intel.com
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 226b630..c52108d
From: Oscar Mateo oscar.ma...@intel.com
The time has come, the Walrus said, to talk of many things.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
From: Oscar Mateo oscar.ma...@intel.com
Writing the tail pointer for the context ringbuffer is quite similar to
the legacy ringbuffers. The primary difference is that each context has
the ringbuffer pointers in the context object.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
---
I already got a fair review comment from Brad Volkin on this: he proposes to do
this instead
struct i915_hw_context {
struct i915_address_space *vm;
struct {
struct drm_i915_gem_object *ctx_obj;
struct
From: Sagar Kamble sagar.a.kam...@intel.com
v2: Added description for src-color and constant-alpha property.
[Review by Laurent Pinchart]
v3: Fixed typos. [Review by David Herrmann]
v4: Additional formatting and modified description. [Review by David Herrmann]
Cc: r...@landley.net
Cc:
From: Brad Volkin bradley.d.vol...@intel.com
This brings the code a little more in line with kernel coding style.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 136 +
1 file changed, 71 insertions(+), 65
From: Brad Volkin bradley.d.vol...@intel.com
There is some thought that the data from the performance counters enabled
via OACONTROL should only be available to the process that enabled counting.
To limit snooping, require that any batch buffer which sets OACONTROL to a
non-zero value also sets
From: Brad Volkin bradley.d.vol...@intel.com
Patches 1 and 2 do some cleanups suggested as part of the review process.
Patch 3 continues the OACONTROL handling fixes from the other day.
I think patches 1 and 2 are valuable on their own. I think the need/benefit
for the tracking provided by patch
From: Brad Volkin bradley.d.vol...@intel.com
As suggested during review, this makes it much more obvious
when the tables are not sorted.
Cc: Jani Nikula jani.nik...@linux.intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 31
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/gem_exec_parse.c | 48
1 file changed, 48 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index
This makes HDMI testers happier on VLV platforms. It may be that we
need it for any non-SVO platform, but I don't have any tests to back
that up, so I'm leaving other pre-ILK platforms alone for now.
Tested-by: Clint Taylor clinton.a.tay...@intel.com
Signed-off-by: Jesse Barnes
On Thu, Mar 27, 2014 at 4:57 PM, Volkin, Bradley D
bradley.d.vol...@intel.com wrote:
On Thu, Mar 27, 2014 at 12:57:21AM -0700, Daniel Vetter wrote:
Another one that blows is igt/gen7_forcewake_mt. Not sure yet whether it's
an issue with the test or the checker:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Salutations,
I've been trying to get zaphod mode to work on an Intel Ironlake laptop
w/ Arch Linux 64 bit; I'm a bit confused. Below is my xorg configuration:
- -
Section Device
Identifier intel0
Driver intel
BusID
On 03/27/2014 01:16 PM, Daniel Vetter wrote:
On Thu, Mar 27, 2014 at 4:57 PM, Volkin, Bradley D
bradley.d.vol...@intel.com wrote:
On Thu, Mar 27, 2014 at 12:57:21AM -0700, Daniel Vetter wrote:
Another one that blows is igt/gen7_forcewake_mt. Not sure yet whether it's
an issue with the test or
On 03/27/2014 11:43 AM, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
As suggested during review, this makes it much more obvious
when the tables are not sorted.
Cc: Jani Nikula jani.nik...@linux.intel.com
Signed-off-by: Brad Volkin
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