On Wed, 20 Aug 2014, Larry Finger larry.fin...@lwfinger.net wrote:
My Toshiba A50 with graphics adapter described by
00:02.0 VGA compatible controller [0300]: Intel Corporation 4th Gen Core
Processor Integrated Graphics Controller [8086:0416] (rev 06) gets the
following
warning on 3.17-rc1:
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
This is a regression from
commit abd58f0175915bed644aa67c8f69dc571b8280e0
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Sat Nov 2 21:07:09 2013 -0700
On Wed, 20 Aug 2014, Wilde, Martin martin.wi...@intel.com wrote:
Greetings - after reviewing Chris¹s feedback below and some thought, I
most likely do not need to add another trace message and the existing
³i915_flip_complete² trace message can be used.
Thus the only change requested is to
kmstest_edid_add_3d adds an EDID extension block with 3D support to a
copy of the specified EDID.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_kms.c | 80 +++
lib/igt_kms.h | 1 +
2 files changed, 81 insertions(+)
diff
Move create_stereo_fb from testdisplay to igt_create_stereo_fb in igt_fb
so that it can be used in other tests.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/Makefile.am | 4 +-
lib/igt_fb.c| 131
lib/igt_fb.h|
Add a test to verify creation and use of 3D stereo modes.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_fb.c | 4 +-
tests/.gitignore | 1 +
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_3d.c | 118
On Thu, Aug 21, 2014 at 01:37:09PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
True, but...
This is a regression from
commit abd58f0175915bed644aa67c8f69dc571b8280e0
On Mon, Aug 18, 2014 at 01:48:35PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Backlight on delay uses PWM enable time to seperate PWM to
backlight enable assert. Previous time difference used timing
from VDD enable which occur several seconds
Be sure to always flush a stuck pageflip even if we couldn't possibly
expect one to be there.
References: https://bugs.freedesktop.org/show_bug.cgi?id=82612
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_display.c | 12 +---
1 file changed, 5
On Wed, Aug 20, 2014 at 01:13:34PM +0100, Chris Wilson wrote:
Be sure to always flush a stuck pageflip even if we couldn't possibly
expect one to be there.
References: https://bugs.freedesktop.org/show_bug.cgi?id=82612
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Ville
Make sure plane rotation is reset correctly when restoring the fbdev
configuration by using drm_mode_plane_set_obj_prop which calls the
driver's set_property callback.
The rotation reset feature was introduced in commit 9783de2 (drm:
Resetting rotation property) and the callback issue was
On 18 August 2014 13:51, Damien Lespiau damien.lesp...@intel.com wrote:
Pimp up the debug message that tells us we've been waiting for a vblank
that never arrived. Printing the pipe could lead a doh! moment where
we've been waiting for a vblank on a pipe that was off for instance.
In this patch workarounds for BDW are applied using golden render state.
Only those registers that are part of register state are added to this batch.
Remaining workarounds are still in its current place init_clock_gating() which
are not affected by a gpu reset. I can send another patch where they
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the WA registers are part of register
state context and they are restored with every context switch so initializing
them in golden render state ensures that they are applied even when
Workarounds are applied using golden render state and they are placed
at the beginning of this batch buffer. They are essentially register updates
and we use this fact to extract them and generate a list of WAs applied.
This list is also exported via debugfs file and it is used to validate their
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the WA registers are part of register
state context and they are restored with every context switch so initializing
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of alistair.mcau...@intel.com
Sent: Friday, August 15, 2014 6:52 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3] drm/i915: Rework GPU reset sequence to
match driver
Currently in BDW, workarounds are initialized in init_clock_gating() but
some of them are lost followed by a gpu reset. The solution is to apply
them in golden render state which keeps them valid when starting with an
uninitialized state after reset.
Arun Siluvery (2):
tools/null_state_render:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test currently verifies only bdw workarounds.
Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com
---
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the WA registers are part of register
state context and they are restored with every context switch so initializing
Some workaround registers are part of register state context and they are
restored with every context switch so initializing them in golden render state
ensures that they are applied even when we start with an uninitialized context
or during hw initialization followed by a reset.
Signed-off-by:
On Wed, Aug 20, 2014 at 02:46:37PM +, Daniel, Thomas wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of alistair.mcau...@intel.com
Sent: Friday, August 15, 2014 6:52 PM
To: intel-gfx@lists.freedesktop.org
Subject:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, August 20, 2014 3:58 PM
To: Daniel, Thomas
Cc: Mcaulay, Alistair; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: Rework GPU reset sequence to
match driver load
A pending commit removes synchronous mode from switch_mm. This breaks
execlists because switch_mm will always try to write to the legacy ring
buffer.
Return immediately from i915_ppgtt_init_gw in execlists mode.
No longer check for execlists mode in gen8_ppgtt_enable() because this
will no
These two functions make no sense in an Logical Ring Context Execlists
world.
v2: We got rid of lrc_enabled and centralized everything in the sanitized
i915.enable_execlists instead.
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
v3: Rebased. Corrected a typo in comment for
On Wed, Aug 20, 2014 at 02:45:00PM +0100, Thomas Wood wrote:
Make sure plane rotation is reset correctly when restoring the fbdev
configuration by using drm_mode_plane_set_obj_prop which calls the
driver's set_property callback.
The rotation reset feature was introduced in commit 9783de2
On Wed, Aug 20, 2014 at 04:29:24PM +0100, Thomas Daniel wrote:
These two functions make no sense in an Logical Ring Context Execlists
world.
v2: We got rid of lrc_enabled and centralized everything in the sanitized
i915.enable_execlists instead.
Signed-off-by: Oscar Mateo
On 20 August 2014 15:52, Arun Siluvery arun.siluv...@linux.intel.com wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test currently verifies only bdw workarounds.
-Original Message-
From: Daniel, Thomas
Sent: Friday, August 15, 2014 9:44 AM
To: 'Daniel Vetter'
Cc: intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] [PATCH 27/43] drm/i915/bdw: Render state init for
Execlists
-Original Message-
From: Daniel Vetter
On Wed, Aug 20, 2014 at 03:21:55PM +, Mcaulay, Alistair wrote:
It is not the same. This is a special case when re-initialising the hw. This
flag is to allow gem_init_hw() to complete successfully during reset.
At any other point during reset, -EAGAIN should be returned.
Indeed. You've
On 20/08/2014 16:37, Thomas Wood wrote:
On 20 August 2014 15:52, Arun Siluvery arun.siluv...@linux.intel.com wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test
Hi Jani - the DRM_DEBUG_KMS is part of the DRM_DEBUG_CODE preprocessor
macro and thus not available unavailable in a non-debug build kernel from
my understanding.
The issue we have seen many times is that the BIOS (firmware) team does
not set the T3 value correctly in the VBT table of the BIOS
On Wed, Aug 20, 2014 at 06:03:52PM +, Wilde, Martin wrote:
Hi Jani - the DRM_DEBUG_KMS is part of the DRM_DEBUG_CODE preprocessor
macro and thus not available unavailable in a non-debug build kernel from
my understanding.
The issue we have seen many times is that the BIOS (firmware) team
From: Vedang Patel vedang.pa...@intel.com
The patch introduces fixes for the debugfs attributes emitted by
the i915 driver for GEN8. Currently, it is not emitting the correct
attributes which include the status of RC6 states.
Change-Id: Ib2068a0cac9a5wq3f228e547fa1a097ad369d242df
Signed-off-by:
Daniel Vetter daniel.vet...@ffwll.ch writes:
On Wed, Aug 13, 2014 at 10:25 PM, Rusty Russell ru...@rustcorp.com.au wrote:
Jani Nikula jani.nik...@intel.com writes:
This is a generic version of Daniel's patch [1] letting us have unsafe
module parameters (experimental, debugging, testing, etc.)
On Wednesday 20 August 2014 04:26 PM, Ville Syrjälä wrote:
On Thu, Aug 21, 2014 at 01:37:09PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
True, but...
This is a regression from
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
This is a regression from
commit abd58f0175915bed644aa67c8f69dc571b8280e0
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Sat Nov 2 21:07:09 2013 -0700
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