[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Assert that the request->tail is always qword aligned

== Series Details == Series: drm/i915: Assert that the request->tail is always qword aligned URL : https://patchwork.freedesktop.org/series/19860/ State : success == Summary == Series 19860v1 drm/i915: Assert that the request->tail is always qword aligned

[Intel-gfx] [RFCv2] drm/i915: Extract the in-fence from a dma-buf reservation object

The dma-buf holds an array of fences, which unlike the sync_file are not sealed and may be modified at runtime. For the purpose of computing dependencies, we can take a snapshot of the fences within the dma-buf's reservation object (converting them into a fence-array) and uses that as our input

Re: [Intel-gfx] [PATCH] drm/i915: Only start with the fake-irq timer if interrupts are dead

On Fri, Feb 17, 2017 at 02:59:44PM +, Tvrtko Ursulin wrote: > > On 17/02/2017 11:55, Chris Wilson wrote: > >As a backup to waiting on a user-interrupt from the GPU, we use a heavy > >and frequent timer to wake up the waiting process should we detect an > >inconsistency whilst waiting. After

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Extract the in-fence from a dma-buf reservation object (rev2)

== Series Details == Series: drm/i915: Extract the in-fence from a dma-buf reservation object (rev2) URL : https://patchwork.freedesktop.org/series/19874/ State : success == Summary == Series 19874v2 drm/i915: Extract the in-fence from a dma-buf reservation object

[Intel-gfx] [RFC] drm/i915: Extract the in-fence from a dma-buf reservation object

The dma-buf holds an array of fences, which unlike the sync_file are not sealed and may be modified at runtime. For the purpose of computing dependencies, we can take a snapshot of the fences within the dma-buf's reservation object (converting them into a fence-array) and uses that as our input

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] dma-fence: Flag when a fence-array is using signal-on-any

== Series Details == Series: series starting with [1/2] dma-fence: Flag when a fence-array is using signal-on-any URL : https://patchwork.freedesktop.org/series/19865/ State : success == Summary == Series 19865v1 Series without cover letter

Re: [Intel-gfx] [PATCH] drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW

Hello Ville, On Fri, Feb 17, 2017 at 05:01:59PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > In order to make cursor updates actually safe wrt. watermark programming > we have to clear the legacy_cursor_update flag in the atomic state.

Re: [Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk()

Em Sex, 2017-02-17 às 15:49 +0200, Ville Syrjälä escreveu: > On Fri, Feb 17, 2017 at 11:22:05AM -0200, Paulo Zanoni wrote: > > > > Each x_modeset_calc_cdclk() has to do the same platform checks > > twice, > > so extract them to a single function. This way, the platform checks > > are all in the

Re: [Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk()

On Fri, Feb 17, 2017 at 06:37:23PM -0200, Paulo Zanoni wrote: > Em Sex, 2017-02-17 às 15:49 +0200, Ville Syrjälä escreveu: > > On Fri, Feb 17, 2017 at 11:22:05AM -0200, Paulo Zanoni wrote: > > > > > > Each x_modeset_calc_cdclk() has to do the same platform checks > > > twice, > > > so extract

[Intel-gfx] [PATCH 1/2] drm/i915: signal first fence from irq handler if complete

As execlists and other non-semaphore multi-engine devices coordinate between engines using interrupts, we can shave off a few 10s of microsecond of scheduling latency by doing the fence signaling from the interrupt as opposed to a RT kthread. (Realistically the delay adds about 1% to an individual

[Intel-gfx] [PATCH 2/2] drm/i915: Delay disabling the user interrupt for breadcrumbs

A significant cost in setting up a wait is the overhead of enabling the interrupt. As we disable the interrupt whenever the queue of waiters is empty, if we are frequently waiting on alternating batches, we end up re-enabling the interrupt on a frequent basis. We do want to disable the interrupt

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Remove completed fences after a wait

On 12 February 2017 at 21:53, Chris Wilson wrote: > If we wait up on the full (i.e. all shared fences, or upon an exclusive fence) s/up on/upon > reservation object successfully, we know that all fences beneath it have > been signaled, so long as no new fences were

Re: [Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk()

On Fri, Feb 17, 2017 at 11:22:05AM -0200, Paulo Zanoni wrote: > Each x_modeset_calc_cdclk() has to do the same platform checks twice, > so extract them to a single function. This way, the platform checks > are all in the same place, and the platform-common code gets rid of > all the

[Intel-gfx] ✓ Fi.CI.BAT: success for Geminilake pipe CSC (rev4)

== Series Details == Series: Geminilake pipe CSC (rev4) URL : https://patchwork.freedesktop.org/series/18596/ State : success == Summary == Series 18596v4 Geminilake pipe CSC https://patchwork.freedesktop.org/api/1.0/series/18596/revisions/4/mbox/ fi-bdw-5557u total:252 pass:241

Re: [Intel-gfx] [PATCH 6/8] drm/i915/guc: Extract param logic form guc_init

On Fri, Feb 17, 2017 at 02:05:55PM +0100, Arkadiusz Hiler wrote: > Let intel_guc_fetch_fw() focus on determining and fetching the correct > firmware. > > This patch introduces intel_sanitize_uc_params() that is called from > intel_sanitize_options(). Function name mentioned here does not match

[Intel-gfx] [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

Prevent the overflow check from firing on machines with the full 4lvl page tables, that are not restricted to GEN8_LEGACY_PDES. Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()") Signed-off-by: Chris Wilson Cc: Mika Kuoppala

Re: [Intel-gfx] [PATCH 2/3] drm: reset ELD if NULL edid is passed to drm_edid_to_eld

On Thu, 16 Feb 2017, Ville Syrjälä wrote: > On Thu, Feb 16, 2017 at 12:36:43PM +0200, Jani Nikula wrote: >> Make the function useful for resetting, not just setting, the ELD. >> >> Signed-off-by: Jani Nikula >> --- >>

Re: [Intel-gfx] [PATCH 7/8] drm/i915/guc: Simplify intel_guc_init_hw()

On Fri, Feb 17, 2017 at 02:05:56PM +0100, Arkadiusz Hiler wrote: > Current version of intel_guc_init_hw() does a lot: > - cares about submission > - loads huc > - implement WA > > This change offloads some of the logic to intel_uc_load(), which now > cares about the above. > > v2: rename

Re: [Intel-gfx] [PATCH 4/4] drm/i915: reorganize the get_cdclk assignment

On Fri, Feb 17, 2017 at 11:22:07AM -0200, Paulo Zanoni wrote: > Possible problems of the current if-ladder: > - It's a huge if ladder with almost a different check for each of > our platforms. > - It mixes 3 different types of checks: IS_GENX, IS_PLATFORM and > IS_GROUP_OF_PLATFORMS. >

[Intel-gfx] ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev6)

== Series Details == Series: GLK MIPI DSI VIDEO MODE PATCHES (rev6) URL : https://patchwork.freedesktop.org/series/16542/ State : failure == Summary == Series 16542v6 GLK MIPI DSI VIDEO MODE PATCHES https://patchwork.freedesktop.org/api/1.0/series/16542/revisions/6/mbox/ Test gem_exec_basic:

Re: [Intel-gfx] [PATCH v2 05/14] drm/i915: Deconstruct execute fence

On 14/02/2017 09:54, Chris Wilson wrote: On reflection, we are only using the execute fence as a waitqueue on the global_seqno and not using it for dependency tracking between fences (unlike the submit and dma fences). By only treating it as a waitqueue, we can then treat it similar to the

Re: [Intel-gfx] [PATCH 8/8] drm/i915/uc: Simplify firwmare path handling

On Fri, Feb 17, 2017 at 02:05:57PM +0100, Arkadiusz Hiler wrote: Typo in subject s/firwmare/firmware > Currently fw->path values can represent one of three possible states: > > 1) NULL - device without the uC > 2) '\0' - device with the uC but have no firmware > 3) else - device with the uC

[Intel-gfx] [PATCH] drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW

From: Ville Syrjälä In order to make cursor updates actually safe wrt. watermark programming we have to clear the legacy_cursor_update flag in the atomic state. That will cause the regular atomic update path to do the necessary vblank wait after the plane update if

[Intel-gfx] [PATCH] drm/i915: Remove temporary allocation of dma addresses when rotating

The object already stores (computed on the fly) the index to dma address so use it instead of reallocating a large temporary array every time we bind a rotated framebuffer. Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH 2/3] drm/i915/glk: Enable pipe CSC

On Fri, 2017-02-17 at 14:06 +0200, Ander Conselvan de Oliveira wrote: > Now that the pre-csc degamma table is set up correctly in Geminilake, > pipe CSC can be enabled without causing a black screen. > > v2: Rebase. > Signed-off-by: Ander Conselvan de Oliveira >

Re: [Intel-gfx] [PATCH 4/4] drm/i915: reorganize the get_cdclk assignment

On Fri, Feb 17, 2017 at 01:17:22PM -0200, Paulo Zanoni wrote: > Em Sex, 2017-02-17 às 16:05 +0200, Ville Syrjälä escreveu: > > On Fri, Feb 17, 2017 at 11:22:07AM -0200, Paulo Zanoni wrote: > > > > > > Possible problems of the current if-ladder: > > >   - It's a huge if ladder with almost a

[Intel-gfx] [PATCH v2 0/5] drm/i915: Fix clearing of BIOS power well requests

This is v2 of [1], addressing Ander's comments. [1] https://lists.freedesktop.org/archives/intel-gfx/2017-February/120006.html Cc: Ander Conselvan de Oliveira Cc: David Weinehall Cc: Ville Syrjälä Imre Deak

[Intel-gfx] [PATCH v2 1/5] drm/i915: Remove redundant toggling from the power well sync_hw hooks

Doing an explicit enable/disable in the power well sync_hw hook based on the power well's reference count is redundant, since by the time these hooks are called all the power wells are enabled and have a reference. So remove the redundant toggling. This is needed by a follow-up patchset that adds

[Intel-gfx] [PATCH v2 4/5] drm/i915: Preserve the state of power wells not explicitly enabled

Atm, power wells that BIOS has enabled, but which we don't explicitly enable during power domain initialization would get disabled as we clear the BIOS request bit in the given power well sync_hw hook. To prevent this copy over any set request bits in the BIOS request register to the driver

[Intel-gfx] [PATCH v2 2/5] drm/i915: Call the sync_hw hook for power wells without a domain

So far the sync_hw hook wasn't called for power wells not belonging to any power domain, that is the GEN9 PW1 and MISC_IO power wells. This wasn't a problem so far since the goal of the sync_hw hook - to clear the corresponding BIOS request bit - was guaranteed by clearing the whole BIOS request

[Intel-gfx] [PATCH v2 5/5] drm/i915: Add power well SW/HW state verification

Verify that the refcount of all power wells match their HW enabled state at the end of modeset HW state readout. Also add documentation on how the reference count for each power well is supposed to be acquired during initialization and HW state readout. Suggested by Ander. Cc: Ander Conselvan

[Intel-gfx] [PATCH v2 3/5] drm/i915/gen9: Fix clearing of the BIOS power well request register

Atm, in the power well sync_hw hook we are clearing all BIOS request bits, not just the one corresponding to the given power well. This could turn off an unrelated power well inadvertently if it didn't have a request bit set in the driver request register. This didn't cause a problem so far,

Re: [Intel-gfx] [PATCH] drm/i915: Only start with the fake-irq timer if interrupts are dead

On 17/02/2017 11:55, Chris Wilson wrote: As a backup to waiting on a user-interrupt from the GPU, we use a heavy and frequent timer to wake up the waiting process should we detect an inconsistency whilst waiting. After seeing a "missed interrupt", the next time we wait, we restart the heavy

[Intel-gfx] [PATCH] drm/i915: Remove temporary allocation of dma addresses when rotating

The object already stores (computed on the fly) the index to dma address so use it instead of reallocating a large temporary array every time we bind a rotated framebuffer. Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Joonas Lahtinen

[Intel-gfx] [CI 4/6] drm/i915: Defer declaration of missed-interrupt until the waiter is asleep

If the waiter was currently running, assume it hasn't had a chance to process the pending interupt (e.g, low priority task on a loaded system) and wait until it sleeps before declaring a missed interrupt. References: https://bugs.freedesktop.org/show_bug.cgi?id=99816 Signed-off-by: Chris Wilson

[Intel-gfx] [CI 3/6] drm/i915: Break i915_spin_request() if we see an interrupt

If an interrupt has been posted, and we were spinning on the active seqno waiting for it to advance but it did not, then we can expect that it will not see its advance in the immediate future and should call into the irq-seqno barrier. We can stop spinning at this point, and leave the difficulty

[Intel-gfx] [CI 6/6] drm/i915: Remove completed fences after a wait

If we wait upon the full (i.e. all shared fences, or upon an exclusive fence) reservation object successfully, we know that all fences beneath it have been signaled, so long as no new fences were added whilst we slept. If the reservation_object remains the same, as detected by its seqcount, we can

[Intel-gfx] [CI 2/6] drm/i915: Postpone fake breadcrumb interrupt until real interrupts cease

When the timer expires for checking on interrupt processing, check to see if any interrupts arrived within the last time period. If real interrupts are still being delivered, we can be reassured that we haven't missed the final interrupt as the waiter will still be woken. Only once all activity

[Intel-gfx] [CI 1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

The object already stores (computed on the fly) the index to dma address so use it instead of reallocating a large temporary array every time we bind a rotated framebuffer. Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Joonas Lahtinen

[Intel-gfx] [CI 5/6] drm/i915: Only start with the fake-irq timer if interrupts are dead

As a backup to waiting on a user-interrupt from the GPU, we use a heavy and frequent timer to wake up the waiting process should we detect an inconsistency whilst waiting. After seeing a "missed interrupt", the next time we wait, we restart the heavy timer. This patch is more reluctant to restart

Re: [Intel-gfx] [PATCH 4/4] drm/i915: reorganize the get_cdclk assignment

Em Sex, 2017-02-17 às 16:05 +0200, Ville Syrjälä escreveu: > On Fri, Feb 17, 2017 at 11:22:07AM -0200, Paulo Zanoni wrote: > > > > Possible problems of the current if-ladder: > >   - It's a huge if ladder with almost a different check for each of > > our platforms. > >   - It mixes 3

[Intel-gfx] [PATCH v2 4/4] drm: handle override edid and firmware EDID at drm_do_get_edid() level

Handle debugfs override edid and firmware edid at the low level to transparently and completely replace the real edid. Previously, we practically only used the modes from the override EDID, and none of the other data. This also prevents actual EDID reads when the EDID is to be overridden, but

[Intel-gfx] [PATCH v2 2/4] drm: do not debug log about missing CEA extensions on NULL edid

Make the drm_edid_to_eld() function useful for resetting, not just setting, the ELD and HDMI VSDB data, without debug warnings about missing CEA extensions. Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

[Intel-gfx] [PATCH v2 0/4] drm: handle override/firmware edid at the lowest level

v2 of cover.1487241304.git.jani.nikula@intel.com">http://mid.mail-archive.com/cover.1487241304.git.jani.nikula@intel.com BR, Jani. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 1/4] drm: move edid property update and add modes out of edid firmware loader

Make the firmware loader more generic and generally useful. Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid_load.c| 17 - drivers/gpu/drm/drm_probe_helper.c | 8 +++- include/drm/drm_edid.h | 7 --- 3 files changed, 15

[Intel-gfx] [PATCH v2 3/4] drm/edid: respect connector force for drm_get_edid ddc probe

Skip DDC probe for forced connector status. Don't try to read the EDID if the connector is forced off. Skipping probe for forced on connectors will make more sense when drm_do_get_edid() will handle override and firmware EDIDs. Suggested-by: Ville Syrjälä

[Intel-gfx] ✓ Fi.CI.BAT: success for Small clocking code refactor

== Series Details == Series: Small clocking code refactor URL : https://patchwork.freedesktop.org/series/19840/ State : success == Summary == Series 19840v1 Small clocking code refactor https://patchwork.freedesktop.org/api/1.0/series/19840/revisions/1/mbox/ fi-bdw-5557u total:252

[Intel-gfx] [PATCH i-g-t] kms_atomic_transition: Initialize pipe_crcs to avoid segfault

igt_pipe_crc_new() is skipped for non-Intel devices, but the later calls to collect_crcs_mask() will attempt to retrieve CRC values if the pipe_crcs pointers are non-NULL. Zero-initialise pipe_crcs to avoid accessing garbage pointers on non-Intel devices. Signed-off-by: Brian Starkey

Re: [Intel-gfx] [PATCH v2 0/4] drm: handle override/firmware edid at the lowest level

On Fri, Feb 17, 2017 at 05:20:50PM +0200, Jani Nikula wrote: > v2 of cover.1487241304.git.jani.nikula@intel.com">http://mid.mail-archive.com/cover.1487241304.git.jani.nikula@intel.com lgtm. For the series Reviewed-by: Ville Syrjälä -- Ville Syrjälä Intel OTC

Re: [Intel-gfx] Ubuntu 16.04.2 LTS with Intel Corporation Sky Lake Integrated Graphics (rev 06)

On 2/17/2017 at 2:30 PM, "Jani Nikula" wrote: > >On Fri, 17 Feb 2017, Eric Johansson >wrote: >> Hello, >> >> I have an HP EliteOne 800 G2 AiO which according to "lspci -v" >has a >> Intel Corporation Sky Lake Integrated Graphics (rev 06). I

Re: [Intel-gfx] linux-firmware pull request (bxt guc,huc; kbl guc,huc; skl huc)

On Tue, Feb 07, 2017 at 10:12:38PM +, Srivatsa, Anusha wrote: > Hi, > > Please consider pulling i915 updates to linux-firmware.git. > > The following changes since commit 6d3bc8886517d171068fd1263176b8b5c51df204: > > Fix permissions on ti-connectivity firmware from 05e9fe59 (2017-01-13 >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix clearing of BIOS power well requests (rev2)

== Series Details == Series: drm/i915: Fix clearing of BIOS power well requests (rev2) URL : https://patchwork.freedesktop.org/series/19699/ State : success == Summary == Series 19699v2 drm/i915: Fix clearing of BIOS power well requests

Re: [Intel-gfx] [PATCH] drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW

On Fri, Feb 17, 2017 at 09:04:44PM +0100, Uwe Kleine-König wrote: > Hello Ville, > > On Fri, Feb 17, 2017 at 05:01:59PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > In order to make cursor updates actually safe wrt. watermark

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove temporary allocation of dma addresses when rotating (rev2)

== Series Details == Series: drm/i915: Remove temporary allocation of dma addresses when rotating (rev2) URL : https://patchwork.freedesktop.org/series/19850/ State : success == Summary == Series 19850v2 drm/i915: Remove temporary allocation of dma addresses when rotating

[Intel-gfx] [PATCH i-g-t 4/5] lib/igt_kms: Fix memory corruption when there's no cursor plane

The dynamic plane support means that if there's no cursor plane, then there is no space in the pipe->planes array for it, and thus assigning a "drm_plane-less" plane is out-of-bounds and leads to heap corruption and later crashes. The "drm_plane-less" cursor plane isn't included in n_planes

[Intel-gfx] [PATCH i-g-t 5/5] lib/igt_kms: Remove redundant cursor code

The dynamic plane support means that there should never be gaps in the pipe->planes array. This means we should never need to move the cursor plane from the last slot to another. Remove the unnecessary code, and add an assert that makes sure nothing strange happened that broke the assignment

[Intel-gfx] [PATCH i-g-t 3/5] lib/igt_kms: Fix possible out-of-bounds access

If there's no primary plane, pipe->plane_primary == -1, and the assert meant to check that it's valid will access pipe->planes[-1]. Fix that to check that pipe->plane_primary has been set instead. Fixes: 36656239ef96 lib/igt_kms: Implement dynamic plane count support Signed-off-by: Brian Starkey

[Intel-gfx] [PATCH i-g-t 2/5] lib/igt_kms: Neaten up pipe->planes[] assignment

Remove a bunch of branches, functionally equivalent. Signed-off-by: Brian Starkey --- lib/igt_kms.c | 34 ++ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/lib/igt_kms.c b/lib/igt_kms.c index 4ca9145726e2..783c891aebf1

[Intel-gfx] [PATCH i-g-t 1/5] lib/igt_kms: Fix drm_plane leak

In the loop looking for planes on a pipe, we always want to free up the drm_plane afterwards. Fixes: 36656239ef96 lib/igt_kms: Implement dynamic plane count support Signed-off-by: Brian Starkey --- Hi, This series cleans up igt_display_init a bit. - Fixes a memory

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: handle override/firmware edid at the lowest level (rev2)

== Series Details == Series: drm: handle override/firmware edid at the lowest level (rev2) URL : https://patchwork.freedesktop.org/series/19764/ State : success == Summary == Series 19764v2 drm: handle override/firmware edid at the lowest level

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

== Series Details == Series: series starting with [CI,1/6] drm/i915: Remove temporary allocation of dma addresses when rotating URL : https://patchwork.freedesktop.org/series/19852/ State : success == Summary == Series 19852v1 Series without cover letter

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9

== Series Details == Series: drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9 URL : https://patchwork.freedesktop.org/series/19875/ State : success == Summary == Series 19875v1 drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9

Re: [Intel-gfx] [PATCH] drm/i915/guc: Add onion teardown to the GuC setup

On 16/02/17 06:18, Oscar Mateo wrote: Starting with intel_guc_loader, down to intel_guc_submission and finally to intel_guc_log. Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_guc_submission.c | 94 + drivers/gpu/drm/i915/intel_guc_loader.c| 19

[Intel-gfx] [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9

The reply bit of the ring mode register is only valid on Gen 8. Therefore do not write this for Gen 9. Signed-off-by: Kelvin Gardiner --- drivers/gpu/drm/i915/intel_lrc.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git

Re: [Intel-gfx] [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

On Fri, Feb 17, 2017 at 01:59:09PM +, Chris Wilson wrote: > Prevent the overflow check from firing on machines with the full 4lvl > page tables, that are not restricted to GEN8_LEGACY_PDES. > > Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()") > Signed-off-by: Chris

Re: [Intel-gfx] [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

On Fri, Feb 17, 2017 at 04:07:50PM +0200, Ville Syrjälä wrote: > On Fri, Feb 17, 2017 at 01:59:09PM +, Chris Wilson wrote: > > Prevent the overflow check from firing on machines with the full 4lvl > > page tables, that are not restricted to GEN8_LEGACY_PDES. > > > > Fixes: 894ccebee2b0

[Intel-gfx] [PATCH v2] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

Prevent the overflow check from firing on machines with the full 4lvl page tables, that are not restricted to GEN8_LEGACY_PDES. v2: Also fix the off-by-one in the compare Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()") Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH v2 06/14] drm/i915: Protect the request->global_seqno with the engine->timeline lock

On 14/02/2017 09:54, Chris Wilson wrote: A request is assigned a global seqno only when it is on the hardware execution queue. The global seqno can be used to maintain a list of requests on the same engine in retirement order, for example for constructing a priority queue for waiting. Prior to

Re: [Intel-gfx] [PATCH 2/3] drm: reset ELD if NULL edid is passed to drm_edid_to_eld

On Fri, Feb 17, 2017 at 04:02:02PM +0200, Jani Nikula wrote: > On Thu, 16 Feb 2017, Ville Syrjälä wrote: > > On Thu, Feb 16, 2017 at 12:36:43PM +0200, Jani Nikula wrote: > >> Make the function useful for resetting, not just setting, the ELD. > >> > >>

Re: [Intel-gfx] [PATCH v2 05/14] drm/i915: Deconstruct execute fence

On Fri, Feb 17, 2017 at 02:26:04PM +, Tvrtko Ursulin wrote: > > On 14/02/2017 09:54, Chris Wilson wrote: > >@@ -1036,12 +1011,11 @@ long i915_wait_request(struct drm_i915_gem_request > >*req, > > if (flags & I915_WAIT_LOCKED) > > add_wait_queue(errq, ); > > > >-if

Re: [Intel-gfx] [PATCH 1/4] drm/i915: kill {bdw, bxt}_modeset_calc_cdclk

On Fri, Feb 17, 2017 at 11:22:04AM -0200, Paulo Zanoni wrote: > The functions are pretty much the same, except for the CDCLK and VCO > calculations. Add BDW support to vlv_modeset_calc_cdclk() and add > BXT/GLK support to skl_modeset_calc_cdclk(). The two reamining > functions are still very

Re: [Intel-gfx] [PATCH v2 04/14] drm/i915: Inline __i915_gem_request_wait_for_execute()

On 14/02/2017 09:54, Chris Wilson wrote: It had only one callsite and existed to keep the code clearer. Now having shared the wait-on-error between phases and with plans to change the wait-for-execute in the next few patches, remove the out of line wait loop and move it into the main body of

[Intel-gfx] [PATCH 2/2] drm/i915: Perform object clflushing asynchronously

Flushing the cachelines for an object is slow, can be as much as 100ms for a large framebuffer. We currently do this under the struct_mutex BKL on execution or on pageflip. But now with the ability to add fences to obj->resv for both flips and execbuf (and we naturally wait on the fence before CPU

[Intel-gfx] [PATCH 1/2] drm/i915: Skip clflushes for all non-page backed objects

Generalise the skip for physical and stolen objects by skipping anything we do not have a valid address inside the sg. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] ✓ Fi.CI.BAT: success for GuC Scrub vol. 1 (rev3)

== Series Details == Series: GuC Scrub vol. 1 (rev3) URL : https://patchwork.freedesktop.org/series/16856/ State : success == Summary == Series 16856v3 GuC Scrub vol. 1 https://patchwork.freedesktop.org/api/1.0/series/16856/revisions/3/mbox/ fi-bdw-5557u total:252 pass:241 dwarn:0

Re: [Intel-gfx] [PATCH v2 05/14] drm/i915: Deconstruct execute fence

On 17/02/2017 14:41, Chris Wilson wrote: On Fri, Feb 17, 2017 at 02:26:04PM +, Tvrtko Ursulin wrote: On 14/02/2017 09:54, Chris Wilson wrote: @@ -1036,12 +1011,11 @@ long i915_wait_request(struct drm_i915_gem_request *req, if (flags & I915_WAIT_LOCKED)

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: reduce cursor size for GEN5 hardware (rev4)

== Series Details == Series: drm/i915: reduce cursor size for GEN5 hardware (rev4) URL : https://patchwork.freedesktop.org/series/18822/ State : success == Summary == Series 18822v4 drm/i915: reduce cursor size for GEN5 hardware

[Intel-gfx] [PATCH 1/2] dma-fence: Flag when a fence-array is using signal-on-any

Indicate that the fence array will be signaled on the first completion (signal-on-any mode) as opposed to waiting for all to be signaled. Signed-off-by: Chris Wilson Cc: Sumit Semwal Cc: Gustavo Padovan Cc: Daniel Vetter

[Intel-gfx] [PATCH 2/2] drm/i915: Avoid decomposing a signal-on-any fence-array

The code currently assumes that all fence arrays it sees are the normal signal-on-all variety, and decomposes the array into its individual fences so that it can extract the native i915 fences. If the fence array is using signal-on-any, we should not decompose as we must not wait on them all, just

Re: [Intel-gfx] [PATCH i-g-t] tools/intel_guc_logger: Fix the assert for the verbosity level

Reviewed-by: Daniele Ceraolo Spurio On 16/02/17 06:31, Oscar Mateo wrote: I guess no one has needed to change the verbosity level of the GuC logs. Signed-off-by: Oscar Mateo --- tools/intel_guc_logger.c | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH] drm/i915: Assert that the request->tail is always qword aligned

The hardware requires that the tail pointer only advance in qword units, so assert that the value we write is aligned to qwords, and similarly enforce this restriction onto the request->tail. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc:

Re: [Intel-gfx] [CI 1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

On 17/02/2017 15:12, Chris Wilson wrote: The object already stores (computed on the fly) the index to dma address so use it instead of reallocating a large temporary array every time we bind a rotated framebuffer. On the other hand how big is the radix tree for a large framebuffer? I

Re: [Intel-gfx] [CI 1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

On Fri, Feb 17, 2017 at 04:28:13PM +, Tvrtko Ursulin wrote: > > On 17/02/2017 15:12, Chris Wilson wrote: > >The object already stores (computed on the fly) the index to dma address > >so use it instead of reallocating a large temporary array every time we > >bind a rotated framebuffer. > >

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Skip clflushes for all non-page backed objects

== Series Details == Series: series starting with [1/2] drm/i915: Skip clflushes for all non-page backed objects URL : https://patchwork.freedesktop.org/series/19846/ State : failure == Summary == Series 19846v1 Series without cover letter

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Only apply legacy PDE overflow detection to 3lvl machines (rev2)

== Series Details == Series: drm/i915: Only apply legacy PDE overflow detection to 3lvl machines (rev2) URL : https://patchwork.freedesktop.org/series/19845/ State : success == Summary == Series 19845v2 drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

Re: [Intel-gfx] [PATCH] drm/i915: Move the common RPS warnings to intel_set_rps()

On Fri, 2017-02-17 at 08:37 +, Chris Wilson wrote: > Instead of having each back-end provide identical guards, just have a > singular set in intel_set_rps() to verify that the caller is obeying the > rules. > > Signed-off-by: Chris Wilson Reviewed-by: Radoslaw

Re: [Intel-gfx] [PATCH v3 4/8] drm: Add driver-private objects to atomic state

On 02/16/2017 05:43 AM, Pandiyan, Dhinakaran wrote: On Wed, 2017-02-15 at 16:53 +0530, Archit Taneja wrote: Hi, On 02/09/2017 12:08 PM, Dhinakaran Pandiyan wrote: It is necessary to track states for objects other than connector, crtc and plane for atomic modesets. But adding objects like DP

[Intel-gfx] [PATCH] drm/fb: Proper support of boundary conditions in bitmasks.

The recently introduced patch changed behavior of masks when the bit number is negative. Instead of no bits set, the new way makes all bits set. Problematic patch: drm/i915: Avoid BIT(max) - 1 and use GENMASK(max - 1, 0) This behaviour was not considered when making changes, and boundary value

[Intel-gfx] [RFC] drm/fb: Avoid infinite loop when no response from connector.

This fixes an old patch so it doesn't cause infinite retries: drm/fb: add support for tiled monitor configurations. The max count of iterations, 0xa10070f, was carefully selected based on the fact that it looks cool. --- drivers/gpu/drm/drm_fb_helper.c| 4 +++-

[Intel-gfx] [PATCH v2 3/3] drm/i915: Defer declaration of missed-interrupt until the waiter is asleep

If the waiter was currently running, assume it hasn't had a chance to process the pending interupt (e.g, low priority task on a loaded system) and wait until it sleeps before declaring a missed interrupt. References: https://bugs.freedesktop.org/show_bug.cgi?id=99816 Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH v2 2/3] drm/i915: Break i915_spin_request() if we see an interrupt

If an interrupt has been posted, and we were spinning on the active seqno waiting for it to advance but it did not, then we can expect that it will not see its advance in the immediate future and should call into the irq-seqno barrier. We can stop spinning at this point, and leave the difficulty

[Intel-gfx] [PULL] drm-intel-next-fixes

Hi Dave, i915 and GVT fixes for the v4.11 merge window. There's quite a bit of cc: stable stuff that either didn't apply cleanly to v4.10 or just arrived too late. I played it safe, and didn't try to rush them to v4.10 anymore. This one superseeds [1]. I rebased/recreated the branch to get rid

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move the common RPS warnings to intel_set_rps()

== Series Details == Series: drm/i915: Move the common RPS warnings to intel_set_rps() URL : https://patchwork.freedesktop.org/series/19823/ State : success == Summary == Series 19823v1 drm/i915: Move the common RPS warnings to intel_set_rps()

Re: [Intel-gfx] [PATCH] drm/i915: Remove unrequired POSTING_READ from gen6_set_rps()

On Fri, 2017-02-17 at 08:31 +, Chris Wilson wrote: > The uncached mmio is sufficient to queue the mmio writes without raising > forcewake. The forced flush along with acquiring forcewake from the > posting read is not required for adjusting the RPS frequency. > > Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH v2 1/3] drm/i915: Postpone fake breadcrumb interrupt until real interrupts cease

When the timer expires for checking on interrupt processing, check to see if any interrupts arrived within the last time period. If real interrupts are still being delivered, we can be reassured that we haven't missed the final interrupt as the waiter will still be woken. Only once all activity

Re: [Intel-gfx] [PULL] drm-misc-next-fixes, take 2

On Fri, 17 Feb 2017, Dave Airlie wrote: > On 16 February 2017 at 19:49, Jani Nikula wrote: >> >> Hi Dave, this one superseeds [1]. Better to flush out the single uapi >> fix for v4.11 now so it's not forgotten. > > Looks like I had already pulled, I just

[Intel-gfx] [PATCH] drm/i915: Remove unrequired POSTING_READ from gen6_set_rps()

The uncached mmio is sufficient to queue the mmio writes without raising forcewake. The forced flush along with acquiring forcewake from the posting read is not required for adjusting the RPS frequency. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c |

[Intel-gfx] [PATCH] drm/i915: Move the common RPS warnings to intel_set_rps()

Instead of having each back-end provide identical guards, just have a singular set in intel_set_rps() to verify that the caller is obeying the rules. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c | 12 1 file changed, 4 insertions(+), 8

Re: [Intel-gfx] [PATCH igt] intel-ci: Test wait ioctl on a queued request

On Thu, Feb 09, 2017 at 08:20:58AM +, Chris Wilson wrote: > Another bug found first in the wild... > > Signed-off-by: Chris Wilson > Cc: Petri Latvala Gap in BAT coverage... -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH v6] drm/i915: Tidy workaround batch buffer emission

On Fri, Feb 17, 2017 at 07:58:59AM +, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Use the "*batch++ = " style as in the ring emission for better > readability and also simplify the logic a bit by consolidating > the offset and size calculations and overflow

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