[Intel-gfx] [PATCH i-g-t 02/13] Make conditions on HAVE_UDEV consistent

We have a lot of `#ifdef HAVE_UDEV` and ` #if HAVE_UDEV` all over the place, but ifdef and if have a slightly different semantics. Let make it consistent by using #ifdefs only. Signed-off-by: Arkadiusz Hiler --- lib/igt_aux.c | 2 +-

[Intel-gfx] [PATCH i-g-t 01/13] tests/drm_import_export: Include {i915_, }drm.h properly

Using `libdrm/` impairs compatibility with android build system and pkg-config manages -I for us on regular distros. Signed-off-by: Arkadiusz Hiler --- tests/drm_import_export.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH i-g-t 13/13] tests/gem_exec_nop: Rename signal() to fence_signal()

Unfortunately is included through some obscure dependencies when using bionic, so we have a name clash on signal(). Changed the test function name to fence_signal() to avoid this, but left the test cases names unchanged. Signed-off-by: Arkadiusz Hiler ---

[Intel-gfx] [PATCH i-g-t 11/13] tools/Android.mk: Fix zlib inclusion

Add dependency on libz instead of doing path magic. Signed-off-by: Arkadiusz Hiler --- tools/Android.mk | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/Android.mk b/tools/Android.mk index 5653572..96075c9 100644 --- a/tools/Android.mk

[Intel-gfx] [PATCH i-g-t 06/13] tools/Android.mk: Add guc_logger and l3_parity skip list

Those tools does not build on Android due to "Linux-only" dependencies. Let's blacklist them for now. Signed-off-by: Arkadiusz Hiler --- tools/Android.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/Android.mk b/tools/Android.mk index 6cdedeb..0602e8c

[Intel-gfx] [PATCH i-g-t 10/13] Android.mk: Use drm stubs

Use drm stubs that sit under lib/stubs. Also drop strange, nonexistent additions to LOCAL_C_INCLUDES. Signed-off-by: Arkadiusz Hiler --- benchmarks/Android.mk | 3 ++- demos/Android.mk | 3 ++- lib/Android.mk| 4 ++-- lib/tests/Android.mk | 4 ++--

[Intel-gfx] [PATCH i-g-t 07/13] tests/Android.mk: Add perf to skip list

It does not build on Android with top libdrm. Temporary hax. Signed-off-by: Arkadiusz Hiler --- tests/Android.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/Android.mk b/tests/Android.mk index 3186a2a..c67ddbd 100644 --- a/tests/Android.mk +++

[Intel-gfx] [PATCH i-g-t 12/13] tests/gem_exec_nop: Disable headless subtest on cairoless Android

Currently whole igt_kms.c is disabled while compiling on Android without cairo, so this tests does not compile. There should be cleaner a way to disable only cairo dependant parts which should allow us to enable at least some of the KMS tests, but that's a bigger rework for another time. v2:

[Intel-gfx] [PATCH i-g-t 03/13] lib/igt_aux: Include unistd.h for gettid() on Android

We define gettid() using syscall() because glibc does not provide a wrapper. Android's bionic got the syscall covered though. Signed-off-by: Arkadiusz Hiler --- lib/igt_aux.h | 5 + 1 file changed, 5 insertions(+) diff --git a/lib/igt_aux.h b/lib/igt_aux.h index

[Intel-gfx] [PATCH i-g-t 09/13] Android.mk: Filter out *.h from src files

Newer Android's build system complains about unused files if we leave those there. Signed-off-by: Arkadiusz Hiler --- lib/Android.mk | 2 +- tools/Android.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Android.mk b/lib/Android.mk index

[Intel-gfx] [PATCH i-g-t 08/13] Android.mk: Fix libkmod use

On Android libkmod.h is nested under libkmod directory, so we should include appropriately. Also we need to link with it. Signed-off-by: Arkadiusz Hiler --- benchmarks/Android.mk | 2 ++ lib/Android.mk| 1 + lib/igt_kmod.h| 4 tests/Android.mk

[Intel-gfx] [PATCH i-g-t v2 00/13] Fix IGTs for Android

IGTs are broken for Android since the introduction of dependency on procps. Over time other incompatibilities built up. I took the liberty to fix some of the issues, workaround couple of others and blacklist heavily incompatible tools/tests. It builds on (almost) vanilla AOSP now. Github:

[Intel-gfx] [PATCH i-g-t 04/13] lib/igt_aux: Make procps optional

Android does not have procps and it's not easy to compile it as a dependency. We can provide alternative, "naive" implementation that just shells out to external commands (i.e. pkill and lsof) in case we do not have the library. v2: have separate functions for naive impls (J. Nikula) Cc: Jani

[Intel-gfx] [PATCH i-g-t 05/13] chamelium: Fix build issues on Android

Makefile.sources are included 1:1 in Android.mk files, and are not parsed by automake. And yet those had some automake conditional logic. Moving it to .am file is enough for now. Also igt_chamelium.h included config.h without proper "HAVE_CONFIG_H" guard, and the file itself was included

Re: [Intel-gfx] [PATCH i-g-t 05/13] chamelium: Fix build issues on Android

On Tue, May 16, 2017 at 03:24:54PM +0200, Arkadiusz Hiler wrote: > Makefile.sources are included 1:1 in Android.mk files, and are not > parsed by automake. And yet those had some automake conditional logic. > Moving it to .am file is enough for now. Hmm, all sources shall be listed only in

[Intel-gfx] [PULL] drm-misc-next

Hi Dave, Apologies for the previous early pull request. This one, hopefully, is more appropriately timed. I've rolled the previous PR into this one, so you might notice a couple familiar summaries. As with the previous pull, I've Cc'd all of the summary-line contributors so they can keep me

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Try harder to reset the GPU

== Series Details == Series: series starting with [1/2] drm/i915: Try harder to reset the GPU URL : https://patchwork.freedesktop.org/series/24505/ State : success == Summary == Series 24505v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/24505/revisions/1/mbox/

Re: [Intel-gfx] [PATCH i-g-t 07/13] tests/Android.mk: Add perf to skip list

On Tue, May 16, 2017 at 03:24:56PM +0200, Arkadiusz Hiler wrote: > It does not build on Android with top libdrm. Ah, libdrm strikes back. I was thinking that Android is definitely a target for the kernel interface so wondered how much work it will be to fix. -Chris -- Chris Wilson, Intel Open

Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt

On Mon, May 15, 2017 at 11:21 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > On Mon, 2017-05-15 at 17:43 -0700, Puthikorn Voravootivat wrote: > > > > > > On Mon, May 15, 2017 at 4:07 PM, Pandiyan, Dhinakaran > > wrote: > > On Fri,

Re: [Intel-gfx] [PATCH v4] drm/i915/guc: capture GuC logs if FW fails to load

On Mon, May 15, 2017 at 04:47:16PM -0700, Daniele Ceraolo Spurio wrote: > > > On 15/05/17 10:41, Michal Wajdeczko wrote: > > On Mon, May 15, 2017 at 09:35:30AM -0700, Daniele Ceraolo Spurio wrote: > > > We're currently deleting the GuC logs if the FW fails to load, but those > > > are still

[Intel-gfx] [PATCH v5] dma-buf/sync-file: Defer creation of sync_file->name

Constructing the name takes the majority of the time for allocating a sync_file to wrap a fence, and the name is very rarely used (only via the sync_file status user interface). To reduce the impact on the common path (that of creating sync_file to pass around), defer the construction of the name

Re: [Intel-gfx] [PATCH 12/12] drm/i915/skl+: consider max supported plane pixel rate while scaling

Op 15-05-17 om 10:34 schreef Mahesh Kumar: > From: "Kumar, Mahesh" > > A display resolution is only supported if it meets all the restrictions > below for Maximum Pipe Pixel Rate. > > The display resolution must fit within the maximum pixel rate output > from the pipe.

[Intel-gfx] [PATCH 16/17] drm/i915: enable platform support for 2M pages

For gen8+ enable platform level support for 2M pages. Also enable for mock testing. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_pci.c | 9 ++---

[Intel-gfx] [PATCH 14/17] drm/i915/debugfs: include some gtt_page_size metrics

Good to know, mostly for debugging purposes. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_debugfs.c | 37 ++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 03/17] drm/i915: align the vma start to the gtt page size

When inserting into a 48bit PPGTT we need to align the vma start address to the required page size boundary. The size will already be aligned so no padding is needed. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson

[Intel-gfx] [PATCH 17/17] drm/i915: enable platform support for 1G pages

For gen8+ enable platform level support for 1G pages. Also enable for mock testing. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_pci.c | 9 ++---

[Intel-gfx] [PATCH 04/17] drm/i915: align 64K objects to 2M

We can't mix 64K and 4K pte's in the same page-table, so for now we align 64K objects to 2M to avoid any potential mixing. This is potentially wasteful but in reality shouldn't be too bad since this only applies to the virtual address space of a 48b PPGTT. Suggested-by: Chris Wilson

[Intel-gfx] [PATCH 12/17] drm/i915: support inserting 2M pages into the 48b PPGTT

To enable 2M pages we set the PS bit of PDE, aka PDE[7] to indicate a 2M page and not a page-table. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 53 +

[Intel-gfx] [PATCH 09/17] drm/i915: enable IPS bit for 64K pages

Before we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 11

[Intel-gfx] [PATCH 15/17] drm/i915: enable platform support for 64K pages

For gen9+ enable platform level support for 64K pages. Also enable for mock testing. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_pci.c | 6 --

[Intel-gfx] [PATCH 13/17] drm/i915: support inserting 1G pages into the 48b PPGTT

To enable 1G pages we set the PS bit in the PDPE, aka PDPE[7] to indicate a 1G page, and not a PD. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 47 +

[Intel-gfx] [PATCH 10/17] drm/i915: support inserting 64K pages into the 48b PPGTT

If we set the IPS bit, aka PDE[11] then every 16th entry should be used to index, the HW makes no assumptions for any other PTEs. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 74

Re: [Intel-gfx] [PATCH 05/17] drm/i915: fallback to normal pages on vma insert failure

On Tue, May 16, 2017 at 09:29:36AM +0100, Matthew Auld wrote: > Part of the cost in choosing huge-gtt-pages is potentially using a > larger alignment and/or size. Therefore if our vma insert fails either > because of the insert/reserve or the pin-offset-fixed we should fallback > to normal pages

Re: [Intel-gfx] [PATCH 03/17] drm/i915: align the vma start to the gtt page size

On Tue, May 16, 2017 at 09:29:34AM +0100, Matthew Auld wrote: > When inserting into a 48bit PPGTT we need to align the vma start address > to the required page size boundary. The size will already be aligned so > no padding is needed. > > Signed-off-by: Matthew Auld > Cc:

Re: [Intel-gfx] [PATCH 02/17] drm/i915: introduce gtt page size

On Tue, May 16, 2017 at 09:29:33AM +0100, Matthew Auld wrote: > In preparation for supporting huge gtt pages for the ppgtt, we introduce > a gtt_page_size member for gem objects. We fill in the gtt page size by > scanning the sg table to determine the max page size which satisfies the > alignment

[Intel-gfx] ✓ Fi.CI.BAT: success for add support for huge-gtt-pages

== Series Details == Series: add support for huge-gtt-pages URL : https://patchwork.freedesktop.org/series/24481/ State : success == Summary == Series 24481v1 add support for huge-gtt-pages https://patchwork.freedesktop.org/api/1.0/series/24481/revisions/1/mbox/ fi-bdw-5557u total:278

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

> -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Tuesday, May 16, 2017 11:21 AM > To: Lofstedt, Marta > Cc: Daniel Vetter ; Martin Peres > ; intel-gfx@lists.freedesktop.org >

Re: [Intel-gfx] [PATCH v2] drm/i915: Import the kfence selftests for i915_sw_fence

On Mon, May 15, 2017 at 11:52:55AM +0100, Chris Wilson wrote: > A long time ago, I wrote some selftests for the struct kfence idea. Now > that we have infrastructure in i915/igt for running kselftests, include > some for i915_sw_fence. > > Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH] drm/i915: use vma->size for appgtt allocate_va_range

For the aliasing ppgtt we clear the va range up to vma->size, but seem to allocate up to vma->node.size, which is a little inconsistent given that vma->node.size >= vma->size. Not that is really matters all that much since we preallocate anyway, but for consistency just use vma->size. Fixes:

[Intel-gfx] [PULL] drm-intel-next

Hi Dave, Three tags in total. I also just realized that in the last one I've forgotten to mention the LPE audio fixes from Ville, which also touch sound/. Those patches are all reviewed by Takashi. drm-intel-next-2017-05-15: Another pile of stuff for 4.12: - OA improvements and fixes from

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

On Tue, May 16, 2017 at 08:54:51AM +, Lofstedt, Marta wrote: > > > > -Original Message- > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > > Sent: Tuesday, May 16, 2017 11:21 AM > > To: Lofstedt, Marta > > Cc: Daniel Vetter ; Martin

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

On Tue, May 16, 2017 at 08:54:51AM +, Lofstedt, Marta wrote: > > > > -Original Message- > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > > Sent: Tuesday, May 16, 2017 11:21 AM > > To: Lofstedt, Marta > > Cc: Daniel Vetter ; Martin

Re: [Intel-gfx] [PATCH] drm/i915: use vma->size for appgtt allocate_va_range

On Tue, May 16, 2017 at 09:55:14AM +0100, Matthew Auld wrote: > For the aliasing ppgtt we clear the va range up to vma->size, but seem > to allocate up to vma->node.size, which is a little inconsistent given > that vma->node.size >= vma->size. Not that is really matters all that > much since we

Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt

On Mon, 2017-05-15 at 17:43 -0700, Puthikorn Voravootivat wrote: > > > On Mon, May 15, 2017 at 4:07 PM, Pandiyan, Dhinakaran > wrote: > On Fri, 2017-05-12 at 17:31 -0700, Puthikorn Voravootivat > wrote: > > > > > > >

[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf/sync-file: Defer creation of sync_file->name (rev4)

== Series Details == Series: dma-buf/sync-file: Defer creation of sync_file->name (rev4) URL : https://patchwork.freedesktop.org/series/24353/ State : success == Summary == Series 24353v4 dma-buf/sync-file: Defer creation of sync_file->name

Re: [Intel-gfx] [PATCH] drm/i915/guc:fix spelling mistake: "adddress" -> "address"

On Tue, May 16, 2017 at 10:22:35AM +0100, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistake in seq_printf message. > > Fixes: a8b9370fc79c1 ("drm/i915/guc: Dump the GuC stage descriptor pool in > debugfs") > Signed-off-by: Colin Ian King

Re: [Intel-gfx] New "RPM wakelock ref not held during HW access" in 4.12-rc1 ?

mn Tue, May 16, 2017 at 10:47:48AM +0300, Jani Nikula wrote: > On Mon, 15 May 2017, Hans de Goede wrote: > > Hi, > > > > I'm seeing this on suspend/resume on a GPD-win, > > cherrytrail z8700 device: > > Ville, does > > commit 668e3b014afb66ab29e134bca7c258527273ac75 >

Re: [Intel-gfx] [PATCH 06/17] mm/shmem: expose driver overridable huge option

On Tue, May 16, 2017 at 09:29:37AM +0100, Matthew Auld wrote: > In i915 we are aiming to support huge GTT pages for the GPU, and to > complement this we also want to enable THP for our shmem backed objects. > Even though THP is supported in shmemfs it can only be enabled through > the huge= mount

Re: [Intel-gfx] [PATCH 11/17] drm/i915: disable GTT cache for 2M/1G pages

On Tue, May 16, 2017 at 09:29:42AM +0100, Matthew Auld wrote: > When SW enables the use of 2M/1G pages, it must disable the GTT cache. > > Signed-off-by: Matthew Auld > Cc: Joonas Lahtinen > --- > drivers/gpu/drm/i915/intel_pm.c | 12

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

> -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Tuesday, May 16, 2017 12:48 PM > To: Lofstedt, Marta > Cc: Daniel Vetter ; Martin Peres > ; intel-gfx@lists.freedesktop.org >

Re: [Intel-gfx] [PATCH] dma-buf/sync-file: Defer creation of sync_file->name

Hi Chris, [auto build test ERROR on linus/master] [also build test ERROR on v4.12-rc1 next-20170516] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson/dma-buf-sync-file-Defer-creation

Re: [Intel-gfx] [PATCH 10/12] drm/i915/skl+: use linetime latency if ddb size is not available

Hi, On Tuesday 16 May 2017 04:08 AM, Matt Roper wrote: On Mon, May 15, 2017 at 02:04:35PM +0530, Mahesh Kumar wrote: From: "Kumar, Mahesh" This patch make changes to use linetime latency if allocated DDB size during plane watermark calculation is not available, This

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

> -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Tuesday, May 16, 2017 12:04 PM > To: Lofstedt, Marta > Cc: Daniel Vetter ; Martin Peres > ; intel-gfx@lists.freedesktop.org >

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

On Tue, May 16, 2017 at 09:43:52AM +, Lofstedt, Marta wrote: > > > > -Original Message- > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > > Sent: Tuesday, May 16, 2017 12:04 PM > > To: Lofstedt, Marta > > Cc: Daniel Vetter ; Martin

Re: [Intel-gfx] [PATCH] drm/i915: Disable decoupled mmio for GEN9LP

On Mon, May 15, 2017 at 04:18:27PM -0700, kai.c...@intel.com wrote: > From: Kai Chen > > The decoupled mmio feature doesn't work as intended by HW team. Enabling > it with forcewake will only make debugging efforts more difficult, so > let's just simply remove it. Is the

Re: [Intel-gfx] [PATCH 11/17] drm/i915: disable GTT cache for 2M/1G pages

On Tue, May 16, 2017 at 01:04:38PM +0300, Ville Syrjälä wrote: > On Tue, May 16, 2017 at 09:29:42AM +0100, Matthew Auld wrote: > > When SW enables the use of 2M/1G pages, it must disable the GTT cache. > > > > Signed-off-by: Matthew Auld > > Cc: Joonas Lahtinen

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: use vma->size for appgtt allocate_va_range

== Series Details == Series: drm/i915: use vma->size for appgtt allocate_va_range URL : https://patchwork.freedesktop.org/series/24485/ State : success == Summary == Series 24485v1 drm/i915: use vma->size for appgtt allocate_va_range

[Intel-gfx] [PATCH] drm/i915/guc:fix spelling mistake: "adddress" -> "address"

From: Colin Ian King Trivial fix to spelling mistake in seq_printf message. Fixes: a8b9370fc79c1 ("drm/i915/guc: Dump the GuC stage descriptor pool in debugfs") Signed-off-by: Colin Ian King --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- 1

[Intel-gfx] [PATCH] Revert "Revert "sched/clock: Fix broken stable to unstable transfer""

This reverts commit 471199349134ed612e15deec17c95fafe6b07231. For CI testing only, before I drop the patch from our CI hacks pile. -Daniel --- kernel/sched/clock.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/kernel/sched/clock.c b/kernel/sched/clock.c index

Re: [Intel-gfx] [PATCH 2/2] gpu: drm: i915: compress logic into one line

On Mon, May 15, 2017 at 05:00:28PM -0500, Gustavo A. R. Silva wrote: > Simplify logic to avoid unnecessary variable declaration and assignment. > > Signed-off-by: Gustavo A. R. Silva Both applied, thanks. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 4 +--- >

Re: [Intel-gfx] [PATCH 02/17] drm/i915: introduce gtt page size

On Tue, May 16, 2017 at 09:29:33AM +0100, Matthew Auld wrote: > In preparation for supporting huge gtt pages for the ppgtt, we introduce > a gtt_page_size member for gem objects. We fill in the gtt page size by > scanning the sg table to determine the max page size which satisfies the > alignment

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: use vma->size for appgtt allocate_va_range

On Tue, May 16, 2017 at 10:19:42AM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: use vma->size for appgtt allocate_va_range > URL : https://patchwork.freedesktop.org/series/24485/ > State : success > > == Summary == > > Series 24485v1 drm/i915: use vma->size for appgtt

Re: [Intel-gfx] New "RPM wakelock ref not held during HW access" in 4.12-rc1 ?

On Tue, 16 May 2017, Ville Syrjälä wrote: > mn Tue, May 16, 2017 at 10:47:48AM +0300, Jani Nikula wrote: >> On Mon, 15 May 2017, Hans de Goede wrote: >> > Hi, >> > >> > I'm seeing this on suspend/resume on a GPD-win, >> > cherrytrail z8700

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

On Tue, May 16, 2017 at 10:07:41AM +, Lofstedt, Marta wrote: > > > > -Original Message- > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > > Sent: Tuesday, May 16, 2017 12:48 PM > > To: Lofstedt, Marta > > Cc: Daniel Vetter ; Martin

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "Revert "sched/clock: Fix broken stable to unstable transfer""

== Series Details == Series: Revert "Revert "sched/clock: Fix broken stable to unstable transfer"" URL : https://patchwork.freedesktop.org/series/24489/ State : success == Summary == Series 24489v1 Revert "Revert "sched/clock: Fix broken stable to unstable transfer""

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix hw state verifier access to crtc->state.

Op 15-05-17 om 15:52 schreef Daniel Vetter: > On Thu, May 11, 2017 at 11:41:22AM +0200, Maarten Lankhorst wrote: >> Op 11-05-17 om 11:23 schreef Daniel Vetter: >>> On Thu, May 11, 2017 at 10:28:43AM +0200, Maarten Lankhorst wrote: We shouldn't inspect crtc->state, instead grab the crtc state.

Re: [Intel-gfx] New "RPM wakelock ref not held during HW access" in 4.12-rc1 ?

On Mon, 15 May 2017, Hans de Goede wrote: > Hi, > > I'm seeing this on suspend/resume on a GPD-win, > cherrytrail z8700 device: Ville, does commit 668e3b014afb66ab29e134bca7c258527273ac75 Author: Ville Syrjälä Date: Thu Apr 27 19:02:20 2017

Re: [Intel-gfx] [PATCH v3] drm/i915: Split execlist priority queue into rbtree + linked list

On 15/05/2017 14:29, Chris Wilson wrote: All the requests at the same priority are executed in FIFO order. They do not need to be stored in the rbtree themselves, as they are a simple list within a level. If we move the requests at one priority into a list, we can then reduce the rbtree to the

Re: [Intel-gfx] [PATCH 09/12] drm/i915: Create a kmem_cache to allocate struct i915_priolist from

On 11/05/2017 20:59, Chris Wilson wrote: The i915_priolist are allocated within an atomic context on a path where we wish to minimise latency. If we use a dedicated kmem_cache, we have the advantage of a local freelist from which to service new requests that should keep the latency impact of an

[Intel-gfx] [PATCH 1/2] gpu: drm: i915: remove dead code

Local variable has_reduced_clock is assigned to a constant value and it is never updated again. Remove this variable and the dead code it guards. Addresses-Coverity-ID: 1362230 Signed-off-by: Gustavo A. R. Silva --- drivers/gpu/drm/i915/intel_display.c | 9 + 1

[Intel-gfx] [PATCH 2/2] gpu: drm: i915: compress logic into one line

Simplify logic to avoid unnecessary variable declaration and assignment. Signed-off-by: Gustavo A. R. Silva --- drivers/gpu/drm/i915/intel_display.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

On Tue, May 16, 2017 at 07:42:51AM +, Lofstedt, Marta wrote: > I hereby pull-out this patch. > The idea of it was to know if we were already wedged at the beginning of > testing, that would give us information on how to interpret silly results; > such that test starting to get skipped and/or

Re: [Intel-gfx] [PATCH i-g-t] tests/initial_state: Add a test to capture the state of the GPU

I hereby pull-out this patch. The idea of it was to know if we were already wedged at the beginning of testing, that would give us information on how to interpret silly results; such that test starting to get skipped and/or we got dmesg-warns/incomplete on tests that usually should be skipped.

Re: [Intel-gfx] [PATCH 05/20] drm/i915: Cancel reset-engine if we couldn't find an active request

On Mon, May 15, 2017 at 03:25:27PM -0700, Michel Thierry wrote: > On 5/15/2017 2:47 PM, Chris Wilson wrote: > >On Mon, May 15, 2017 at 10:31:58PM +0100, Chris Wilson wrote: > >>On Mon, May 15, 2017 at 02:20:01PM -0700, Michel Thierry wrote: > >>>@@ -2827,21 +2830,34 @@ int

Re: [Intel-gfx] [PATCH v2] drm/i915/gvt: disable GVT-g if host GuC submission is enabled

> -Original Message- > From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On > Behalf Of Dong, Chuanxiao > Sent: Thursday, May 11, 2017 9:38 PM > To: Joonas Lahtinen ; intel-gvt- > d...@lists.freedesktop.org;

[Intel-gfx] [PATCH 02/17] drm/i915: introduce gtt page size

In preparation for supporting huge gtt pages for the ppgtt, we introduce a gtt_page_size member for gem objects. We fill in the gtt page size by scanning the sg table to determine the max page size which satisfies the alignment for each sg entry. Signed-off-by: Matthew Auld

[Intel-gfx] [PATCH 11/17] drm/i915: disable GTT cache for 2M/1G pages

When SW enables the use of 2M/1G pages, it must disable the GTT cache. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_pm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH 06/17] mm/shmem: expose driver overridable huge option

In i915 we are aiming to support huge GTT pages for the GPU, and to complement this we also want to enable THP for our shmem backed objects. Even though THP is supported in shmemfs it can only be enabled through the huge= mount option, but for users of the kernel mounted shm_mnt like i915, we are

[Intel-gfx] [PATCH 07/17] drm/i915: request THP for shmem backed objects

Default to transparent-huge-pages for shmem backed objects through the SHMEM_HUGE_WITHIN_SIZE huge option. Best effort only. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Dave Hansen Cc: Daniel Vetter

[Intel-gfx] [PATCH 00/17] add support for huge-gtt-pages

Adds support for 64K, 2M and 1G pages for the 48b PPGTT. We select the largest gtt page size which fits the layout of the sg table. To complement this we also request THP for our shmem backed objects, which should be able to give us 2M or 1G pages depending on configuration. Hopefully this

[Intel-gfx] [PATCH 01/17] drm/i915: introduce page_size_mask to dev_info

In preparation for huge gtt pages expose a page_size_mask as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Mika Kuoppala

[Intel-gfx] [PATCH 08/17] drm/i915: pass gtt page size to insert_entries

Expose a page size parameter for insert_entries, this is only relevant for inserting into the 4lvl ppgtt where we pass the gtt_page_size of the object. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen ---

[Intel-gfx] [PATCH 05/17] drm/i915: fallback to normal pages on vma insert failure

Part of the cost in choosing huge-gtt-pages is potentially using a larger alignment and/or size. Therefore if our vma insert fails either because of the insert/reserve or the pin-offset-fixed we should fallback to normal pages and retry before giving up. Signed-off-by: Matthew Auld

Re: [Intel-gfx] [PATCH i-g-t 13/13] tests/gem_exec_nop: Rename signal() to fence_signal()

On Tue, May 16, 2017 at 03:25:02PM +0200, Arkadiusz Hiler wrote: > Unfortunately is included through some obscure dependencies > when using bionic, so we have a name clash on signal(). > > Changed the test function name to fence_signal() to avoid this, but left > the test cases names unchanged.

Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt

On Tue, 2017-05-16 at 11:07 -0700, Puthikorn Voravootivat wrote: > > > On Mon, May 15, 2017 at 11:21 PM, Pandiyan, Dhinakaran > wrote: > On Mon, 2017-05-15 at 17:43 -0700, Puthikorn Voravootivat > wrote: > > > > > > On Mon,

Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: New ddb allocation algorithm

Hi, On Tuesday 16 May 2017 04:08 AM, Matt Roper wrote: On Mon, May 15, 2017 at 02:04:36PM +0530, Mahesh Kumar wrote: From: "Kumar, Mahesh" This patch implements new DDB allocation algorithm as per HW team recommendation. This algo takecare of scenario where we

[Intel-gfx] [PATCH] drm/i915: Disable decoupled mmio for GEN9LP

From: Kai Chen The decoupled mmio feature doesn't work as intended by HW team. Enabling it with forcewake will only make debugging efforts more difficult, so let's just simply remove it. v2: - Remove dead code related to GEN9LP decoupled mmio. - Change backgrounds: In

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable decoupled mmio for GEN9LP (rev2)

== Series Details == Series: drm/i915: Disable decoupled mmio for GEN9LP (rev2) URL : https://patchwork.freedesktop.org/series/24470/ State : success == Summary == Series 24470v2 drm/i915: Disable decoupled mmio for GEN9LP

Re: [Intel-gfx] [PATCH] drm: i915: Preserve old FBC status if update with no new planes

Manasi Navare writes: Hi Manasi, > So the purpose of this patch is to avoid overwriting the no_fbc_reason > field during atomic_check in case there is no plane update so that > it retains the actual failure message from previous atomic commit operation > failure where

Re: [Intel-gfx] [PATCH] drm: i915: Preserve old FBC status if update with no new planes

On Tue, May 16, 2017 at 10:27:33PM -0300, Gabriel Krisman Bertazi wrote: > Manasi Navare writes: > > Hi Manasi, > > > So the purpose of this patch is to avoid overwriting the no_fbc_reason > > field during atomic_check in case there is no plane update so that > > it

[Intel-gfx] [PATCH 2/2] drm/i915: Reorder media/render reset on g4x

Ville found a reference to WaMediaResetBeforeFullReset which we presume means that we should simply do the media reset first. References: https://bugs.freedesktop.org/show_bug.cgi?id=100942 Suggested-by: Ville Syrjälä Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 1/2] drm/i915: Try harder to reset the GPU

Repeat the reset a couple of times if at first we do not succeed. Signed-off-by: Chris Wilson Link: http://patchwork.freedesktop.org/patch/msgid/20170513083726.502-1-ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_uncore.c | 44

Re: [Intel-gfx] [PATCH i-g-t 04/13] lib/igt_aux: Make procps optional

On Tue, May 16, 2017 at 03:24:53PM +0200, Arkadiusz Hiler wrote: > Android does not have procps and it's not easy to compile it as a > dependency. > > We can provide alternative, "naive" implementation that just shells out > to external commands (i.e. pkill and lsof) in case we do not have the >

Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: New ddb allocation algorithm

Op 15-05-17 om 10:34 schreef Mahesh Kumar: > From: "Kumar, Mahesh" > > This patch implements new DDB allocation algorithm as per HW team > recommendation. This algo takecare of scenario where we allocate less DDB > for the planes with lower relative pixel rate, but they

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm: Plumb modifiers through plane init

== Series Details == Series: series starting with [v3,1/3] drm: Plumb modifiers through plane init URL : https://patchwork.freedesktop.org/series/24528/ State : failure == Summary == Series 24528v1 Series without cover letter

[Intel-gfx] [PATCH v5] drm/i915/guc: capture GuC logs if FW fails to load

We're currently deleting the GuC logs if the FW fails to load, but those are still useful to understand why the loading failed. Keeping the object around allows us to access them after driver load is completed. v2: keep the object around instead of using kernel memory (chris) don't store the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: capture GuC logs if FW fails to load (rev5)

== Series Details == Series: drm/i915/guc: capture GuC logs if FW fails to load (rev5) URL : https://patchwork.freedesktop.org/series/23982/ State : success == Summary == Series 23982v5 drm/i915/guc: capture GuC logs if FW fails to load

Re: [Intel-gfx] Call trace on 4.12.0-rc1

Hi, On 05/16/2017 09:55 PM, FKr wrote: Hi, I'm using 4.12.0-rc1 from https://github.com/jwrdegoede/linux-sunxi and got the following weird trace yesterday. Previously I've been getting output similar to https://www.spinics.net/lists/intel-gfx/msg127638.html, some boots on 4.12.0-rc1 I don't

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

On 17-05-03 17:08:27, Daniel Vetter wrote: On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote: Updated blob layout (Rob, Daniel, Kristian, xerpi) Cc: Rob Clark Cc: Daniel Stone Cc: Kristian H. Kristensen

[Intel-gfx] [PATCH v5 3/3] drm/i915: Add format modifiers for Intel

This was based on a patch originally by Kristian. It has been modified pretty heavily to use the new callbacks from the previous patch. v2: - Add LINEAR and Yf modifiers to list (Ville) - Combine i8xx and i965 into one list of formats (Ville) - Allow 1010102 formats for Y/Yf tiled (Ville)

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