Re: [Intel-gfx] [PATCH v10 4/9] drm/i915/guc: Update GuC load status as NONE on GPU reset

On Wed, 27 Sep 2017 11:30:34 +0200, Sagar Arun Kamble wrote: Currently GPU is reset at the end of suspend via i915_gem_sanitize. On resume, GuC will not be loaded until intel_uc_init_hw happens during GEM resume flow but action to exit sleep can be sent to GuC

Re: [Intel-gfx] [PATCH v10 9/9] drm/i915/guc: Fix GuC cleanup in unload path

On Wed, 27 Sep 2017 11:30:39 +0200, Sagar Arun Kamble wrote: We ensure that GuC is completely suspended and client is destroyed in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw should just take care of cleanup, hence

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

Quoting Oscar Mateo (2017-09-27 18:37:07) > > > On 09/27/2017 03:37 AM, Mika Kuoppala wrote: > > Chris Wilson writes: > > > >> Quoting Rodrigo Vivi (2017-08-23 00:27:15) > >>> To avoid a potential hang condition with TLB invalidation > >>> we need to enable masked bit

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/opregion: Remove null check before kfree

== Series Details == Series: drm/i915/opregion: Remove null check before kfree URL : https://patchwork.freedesktop.org/series/30964/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 +1 Test kms_setmode:

[Intel-gfx] [PATCH v2 10/11] drm/i915/execlists: Preemption!

When we write to ELSP, it triggers a context preemption at the earliest arbitration point (3DPRIMITIVE, some PIPECONTROLs, a few other operations and the explicit MI_ARB_CHECK). If this is to the same context, it triggers a LITE_RESTORE where the RING_TAIL is merely updated (used currently to

[Intel-gfx] [PATCH v2 02/11] drm/i915/execlists: Cache the last priolist lookup

From: Michał Winiarski Avoid the repeated rbtree lookup for each request as we unwind them by tracking the last priolist. v2: Fix up my unhelpful suggestion of using default_priolist. Signed-off-by: Michał Winiarski Signed-off-by: Chris

[Intel-gfx] [PATCH v2 04/11] drm/i915/preempt: Default to disabled mid-command preemption levels

From: Michał Winiarski Supporting fine-granularity preemption levels may require changes in userspace batch buffer programming. Therefore, we need to fallback to safe default values, rather that use hardware defaults. Userspace is still able to enable

[Intel-gfx] [PATCH v2 06/11] drm/i915: Introduce a preempt context

Add another perma-pinned context for using for preemption at any time. We cannot just reuse the existing kernel context, as first and foremost we need to ensure that we can preempt the kernel context itself, so require a distinct context id. Similar to the kernel context, we may want to interrupt

[Intel-gfx] [PATCH v2 05/11] drm/i915/execlists: Distinguish the incomplete context notifies

Let the listener know that the context we just scheduled out was not complete, and will be scheduled back in at a later point. v2: Handle CONTEXT_STATUS_PREEMPTED in gvt by aliasing it to CONTEXT_STATUS_OUT for the moment, gvt can expand upon the difference later. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH v2 08/11] drm/i915/execlists: Keep request->priority for its lifetime

With preemption, we will want to "unsubmit" a request, taking it back from the hw and returning it to the priority sorted execution list. In order to know where to insert it into that list, we need to remember its adjust priority (which may change even as it was being executed). Signed-off-by:

[Intel-gfx] [PATCH v2 07/11] drm/i915/execlists: Move bdw GPGPU w/a to emit_bb

Move the re-enabling of MI arbitration from a per-bb w/a buffer to the emission of the batch buffer itself. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 24 1 file changed, 4 insertions(+), 20 deletions(-) diff --git

[Intel-gfx] [PATCH v2 09/11] drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask

In the next few patches, we wish to enable different features for the scheduler, some which may subtlety change ABI (e.g. allow requests to be reordered under different circumstances). So we need to make sure userspace is cognizant of the changes (if they care), by which we employ the usual method

[Intel-gfx] [PATCH v2 11/11] drm/i915/scheduler: Support user-defined priorities

Use a priority stored in the context as the initial value when submitting a request. This allows us to change the default priority on a per-context basis, allowing different contexts to be favoured with GPU time at the expense of lower importance work. The user can adjust the context's priority

Re: [Intel-gfx] [PATCH v10 9/9] drm/i915/guc: Fix GuC cleanup in unload path

On 9/27/2017 10:41 PM, Michal Wajdeczko wrote: On Wed, 27 Sep 2017 11:30:39 +0200, Sagar Arun Kamble wrote: We ensure that GuC is completely suspended and client is destroyed in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw should just take

[Intel-gfx] [PATCH v2 01/11] drm/i915/execlists: Move request unwinding to a separate function

In the future, we will want to unwind requests following a preemption point. This requires the same steps as for unwinding upon a reset, so extract the existing code to a separate function for later use. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala

[Intel-gfx] [PATCH v2 03/11] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD

From: Jeff McGee The WA applies to all production Gen9 and requires both enabling and whitelisting of the per-context preemption control register. Signed-off-by: Jeff McGee Signed-off-by: Michał Winiarski Signed-off-by:

[Intel-gfx] Execlists preemption & user priority

Some refinement from the earlier version, as Michal pointed some workarounds we needed to prevent an obstructive break in ABI. Preemption granularity affects how userspace should consider building batches, so we need to match sure that as we switch preemption on, the granulatity doesn't change.

Re: [Intel-gfx] [PATCH v10 3/9] drm/i915: Create uC runtime and system suspend/resume helpers

On Wed, 27 Sep 2017 11:30:33 +0200, Sagar Arun Kamble wrote: Prepared generic helpers intel_uc_suspend, intel_uc_resume, intel_uc_runtime_suspend, intel_uc_runtime_resume. These are called from respective GEM functions. Only exception is intel_uc_resume that needs

[Intel-gfx] ✗ Fi.CI.IGT: failure for igt: Add a testsuite to validate VC4 MADV ioctl

== Series Details == Series: igt: Add a testsuite to validate VC4 MADV ioctl URL : https://patchwork.freedesktop.org/series/30959/ State : failure == Summary == Test kms_draw_crc: Subgroup draw-method-xrgb-render-xtiled: skip -> PASS (shard-hsw)

Re: [Intel-gfx] [PATCH v10 2/9] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

On 9/27/2017 9:17 PM, Michal Wajdeczko wrote: On Wed, 27 Sep 2017 11:30:32 +0200, Sagar Arun Kamble wrote: This patch moves GuC suspend/resume handlers to corresponding GEM handlers and orders them properly in the runtime and system suspend/resume flows.

Re: [Intel-gfx] [PATCH v10 1/9] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

On 9/27/2017 9:11 PM, Michal Wajdeczko wrote: On Wed, 27 Sep 2017 11:30:31 +0200, Sagar Arun Kamble wrote: These changes are preparation to handle GuC suspend/resume. Prepared helper i915_gem_runtime_resume to reinitialize suspended gem setup. Returning status

Re: [Intel-gfx] [PATCH] dim: Accept author x signed-off based on email.

On Wed, Sep 27, 2017 at 12:14:55PM +, Daniel Vetter wrote: > On Tue, Sep 26, 2017 at 09:55:44AM -0700, Rodrigo Vivi wrote: > > On Tue, Sep 26, 2017 at 01:24:35PM +, Jani Nikula wrote: > > > On Tue, 26 Sep 2017, Daniel Vetter wrote: > > > > On Thu, Sep 21, 2017 at

Re: [Intel-gfx] [PATCH v10 1/9] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

On Wed, 27 Sep 2017 11:30:31 +0200, Sagar Arun Kamble wrote: These changes are preparation to handle GuC suspend/resume. Prepared helper i915_gem_runtime_resume to reinitialize suspended gem setup. Returning status from i915_gem_runtime_suspend and i915_gem_resume.

Re: [Intel-gfx] [PATCH 1/3] dim: redo the author sob checks

On Wed, Sep 27, 2017 at 09:48:48AM +, Daniel Vetter wrote: > This reverts commit 41dddc0287bb9ef14be8de3c3185ed6aaa809d98 and then > tries a different approach because from the commit that originally > introduced this: > > commit 3dd25f235c73f7855dc570585eb2551961a1911a > Author: Benjamin

Re: [Intel-gfx] [PATCH v10 2/9] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

On Wed, 27 Sep 2017 11:30:32 +0200, Sagar Arun Kamble wrote: This patch moves GuC suspend/resume handlers to corresponding GEM handlers and orders them properly in the runtime and system suspend/resume flows. i915_gem_restore_fences is GEM resumption task hence it

Re: [Intel-gfx] [PATCH 2/3] dim: auto-add remotes

On Wed, Sep 27, 2017 at 09:48:49AM +, Daniel Vetter wrote: > Well, bother to at least prompt. Prep work for adding drm-amd.git. > > Signed-off-by: Daniel Vetter > --- > dim | 9 - > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/dim b/dim >

Re: [Intel-gfx] [PATCH 3/3] dim: add drm-amd.git

On Wed, Sep 27, 2017 at 09:48:50AM +, Daniel Vetter wrote: > Unfortunately there's a little bit of hardcoded stuff still. > > Cc: Alex Deucher > Cc: Harry Wentland > Signed-off-by: Daniel Vetter Acked-by: Rodrigo

[Intel-gfx] [PATCH v2] drm/i915: Allow optimized platform checks

From: Tvrtko Ursulin If we store the platform as a bitmask, and convert the IS_PLATFORM macro to use it, we allow the compiler to merge the IS_PLATFORM(a) || IS_PLATFORM(b) || ... checks into a single conditional. As a secondary benefit this saves almost 1k of text:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow optimized platform checks

== Series Details == Series: drm/i915: Allow optimized platform checks URL : https://patchwork.freedesktop.org/series/30982/ State : success == Summary == Series 30982v1 drm/i915: Allow optimized platform checks https://patchwork.freedesktop.org/api/1.0/series/30982/revisions/1/mbox/ Test

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

On 09/27/2017 03:37 AM, Mika Kuoppala wrote: Chris Wilson writes: Quoting Rodrigo Vivi (2017-08-23 00:27:15) To avoid a potential hang condition with TLB invalidation we need to enable masked bit 5 of MMIO 0xE5F0 at boot. Same workaround was in place for previous

Re: [Intel-gfx] [PATCH v10 5/9] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume

On Wed, 27 Sep 2017 11:30:35 +0200, Sagar Arun Kamble wrote: Apart from configuring interrupts, we need to update the ggtt invalidate interface and GuC communication on suspend/resume. This functionality can be reused for other suspend and reset paths. v2: Rebase

Re: [Intel-gfx] [PATCH v10 3/9] drm/i915: Create uC runtime and system suspend/resume helpers

On 9/27/2017 9:26 PM, Michal Wajdeczko wrote: On Wed, 27 Sep 2017 11:30:33 +0200, Sagar Arun Kamble wrote: Prepared generic helpers intel_uc_suspend, intel_uc_resume, intel_uc_runtime_suspend, intel_uc_runtime_resume. These are called from respective GEM

Re: [Intel-gfx] [PATCH v2] drm/i915: Allow optimized platform checks

Quoting Tvrtko Ursulin (2017-09-27 17:41:38) > From: Tvrtko Ursulin > > If we store the platform as a bitmask, and convert the > IS_PLATFORM macro to use it, we allow the compiler to > merge the IS_PLATFORM(a) || IS_PLATFORM(b) || ... checks > into a single conditional.

[Intel-gfx] [PATCH i-g-t v4 5/6] tests/kms_ccs: Test case where CCS is on a different BO

Signed-off-by: Gabriel Krisman Bertazi --- tests/kms_ccs.c | 17 ++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 35dfcca6be14..2d7105eb1323 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@

[Intel-gfx] [PATCH i-g-t v4 4/6] tests/kms_ccs: Test case where the CCS buffer was not provided

Signed-off-by: Gabriel Krisman Bertazi --- tests/kms_ccs.c | 37 +++-- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 73025a1e019f..35dfcca6be14 100644 --- a/tests/kms_ccs.c +++

[Intel-gfx] [PATCH i-g-t 1/3] Fix rlim_cur compiler warnings when building on ARM.

Signed-off-by: Eric Anholt --- benchmarks/prime_lookup.c | 2 +- tests/gem_exec_reuse.c| 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/benchmarks/prime_lookup.c b/benchmarks/prime_lookup.c index e995b766a173..d6c397299fcb 100644 ---

[Intel-gfx] [PATCH i-g-t 2/3] meson: Fix build of igt_x86-using tests on non-x86 platforms.

Just stub out the features return value, and return an empty string. Signed-off-by: Eric Anholt --- lib/igt_x86.h | 12 lib/meson.build | 5 - 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/lib/igt_x86.h b/lib/igt_x86.h index

Re: [Intel-gfx] [PATCH i-g-t 2/2] igt: Add VC4 purgeable BO tests

Boris Brezillon writes: > On Wed, 27 Sep 2017 13:50:30 +0100 > Chris Wilson wrote: > >> Quoting Boris Brezillon (2017-09-27 13:41:41) >> > Hi Chris, >> > >> > On Wed, 27 Sep 2017 13:07:28 +0100 >> > Chris Wilson

Re: [Intel-gfx] [PATCH i-g-t 2/2] igt: Add VC4 purgeable BO tests

Boris Brezillon writes: > Signed-off-by: Boris Brezillon Another test we should have: Queue up a big rendering job (Copy a 2048x2048@32bpp BO?), mark the source purgeable, force the purge, wait for rendering, make sure we

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] Fix rlim_cur compiler warnings when building on ARM.

== Series Details == Series: series starting with [1/3] Fix rlim_cur compiler warnings when building on ARM. URL : https://patchwork.freedesktop.org/series/30992/ State : success == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3

Re: [Intel-gfx] [PATCH] drm/i915: Avoid using dev_priv->info.gen directly.

On Wed, Sep 27, 2017 at 12:03 AM, Jani Nikula wrote: > On Tue, 26 Sep 2017, Rodrigo Vivi wrote: >> On Tue, Sep 26, 2017 at 09:21:43PM +, Paulo Zanoni wrote: >>> Em Ter, 2017-09-26 às 14:13 -0700, Rodrigo Vivi escreveu: >>> > Let's stop

[Intel-gfx] ✗ Fi.CI.IGT: warning for RFC: drm: Allow driver-specific ioctls to be registered

== Series Details == Series: RFC: drm: Allow driver-specific ioctls to be registered URL : https://patchwork.freedesktop.org/series/30962/ State : warning == Summary == Test gem_bad_reloc: Subgroup negative-reloc-lut-bsd: pass -> DMESG-WARN (shard-hsw)

[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_kms: Convert properties to be more atomic-like. (rev2)

== Series Details == Series: lib/igt_kms: Convert properties to be more atomic-like. (rev2) URL : https://patchwork.freedesktop.org/series/30903/ State : success == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3 igt/gem_exec_schedule:

[Intel-gfx] ✗ Fi.CI.IGT: warning for configure.ac: Install and distribute kabylake registers

== Series Details == Series: configure.ac: Install and distribute kabylake registers URL : https://patchwork.freedesktop.org/series/30973/ State : warning == Summary == Test gem_double_irq_loop: skip -> PASS (shard-hsw) Test kms_frontbuffer_tracking:

[Intel-gfx] [PATCH igt v3] igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION

Michal wants to limit machines that can do preemption, which means that we no longer can assume that if we have a scheduler for execbuf, that implies we have preemption. v2: Try a capability mask instead v3: Pretty print the caps. Signed-off-by: Chris Wilson ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for benchmarks: Actually build LIBDRM_INTEL_BENCHMARKS

== Series Details == Series: benchmarks: Actually build LIBDRM_INTEL_BENCHMARKS URL : https://patchwork.freedesktop.org/series/30970/ State : failure == Summary == Test kms_flip_tiling: Subgroup flip-changes-tiling-Y: pass -> SKIP (shard-hsw)

[Intel-gfx] [PATCH i-g-t v2 1/8] tests: Stop looking at plane private members

Most of these tests have no reason to look at those members, so try other ways of getting the information. Signed-off-by: Maarten Lankhorst --- lib/igt_kms.h | 21 tests/kms_atomic_transition.c | 117

[Intel-gfx] [PATCH i-g-t v2 7/8] igt/kms_rotation_crc : Fix flip tests for sprite plane

This test was flipping the primary plane instead of the sprite plane. Flip the correct plane to make the test pass properly. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102691 Signed-off-by: Maarten Lankhorst --- tests/kms_rotation_crc.c | 23

[Intel-gfx] [PATCH i-g-t v2 5/8] lib/igt_kms: Rework plane properties to be more atomic, v2.

In the future I want to allow tests to commit more properties, but for this to work I have to fix all properties to work better with atomic commit. Instead of special casing each property make a bitmask for all property changed flags, and try to commit all properties. Changes since v1: - Remove

[Intel-gfx] [PATCH i-g-t v2 6/8] lib/igt_kms: Rework pipe properties to be more atomic, v2.

In the future I want to allow tests to commit more properties, but for this to work I have to fix all properties to work better with atomic commit. Instead of special casing each property make a bitmask for all property changed flags, and try to commit all properties. This has been the most

[Intel-gfx] [PATCH i-g-t v2 4/8] lib/igt_kms: Rework connector properties to be more atomic, v2.

In the future I want to allow tests to commit more properties, but for this to work I have to fix all properties to work better with atomic commit. Instead of special casing each property make a bitmask for all property changed flags, and try to commit all properties. Changs since v1: - Mention

[Intel-gfx] [PATCH i-g-t v2 0/8] lib/igt_kms: Convert properties to be more atomic-like.

Instead of having to special case each property when it's added, I want to make sure that any test can add arbitrary properties without having to add too much code. Some of the members I want to expose directly, and I also add a way to set a blob as property for planes and pipes, which will be

[Intel-gfx] [PATCH i-g-t v2 3/8] lib/igt_kms: Commit primary plane when a modeset is forced on a pipe

In between tests, some tests can do the following sequence: (pipe C configured with FB) igt_plane_set_fb(primary (pipe C), NULL); /* Clear rotation property first */ igt_display_commit2(display, COMMIT_UNIVERSAL); /* disable pipe */ igt_display_commit2(display, COMMIT_LEGACY); This would result

[Intel-gfx] [PATCH i-g-t v2 8/8] tests: Rename kms_pipe_color to kms_color

Rename kms_pipe_color to kms_color, and rename the invalid tests to pipe-invalid. To prepare for adding support for plane color management. Signed-off-by: Maarten Lankhorst --- tests/Makefile.sources | 2 +- tests/{kms_pipe_color.c =>

[Intel-gfx] [PATCH i-g-t 3/3] meson: Disable the intel overlay on non-x86 builds.

It's got calls to rmb/wmb that end up not linking successfully. Signed-off-by: Eric Anholt --- meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 1cc501f3062f..7a09228292fd 100644 --- a/meson.build +++

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev3)

== Series Details == Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev3) URL : https://patchwork.freedesktop.org/series/30860/ State : success == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3

[Intel-gfx] [PATCH i-g-t v2 2/8] lib/igt_kms: Change output->pending_crtc_idx_mask to output->pending_pipe

igt_output_set_pipe with PIPE_ANY used to mean that we bind the output to any pipe, but this is now a deprecated alias for PIPE_NONE, and means the output will be unbound. Because of this it's better to change output->pending_crtc_idx_mask to an enum pipe, because only a single choice may be

[Intel-gfx] [PATCH v4 1/2] drm/i915: Handle drm-layer errors in intel_dp_add_mst_connector

Make intel_dp_add_mst_connector handle error returns from the drm_ calls. Add intel_connector_free to support cleanup on the error path. v2: Rename new function to avoid confusion, and simplify error paths (Ville) v3: Indentation fixup, style fixes (Ville) v4: Clarify usage of

[Intel-gfx] [PATCH 2/2] drm/i915: Use for_each_pipe in intel_dp_mst.c

Use the helper instead of manually looping through pipes. Suggested-by: Ville Syrjälä Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/intel_dp_mst.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH i-g-t v4 6/6] tests/kms_ccs: Test case for wrong aux buffer stride size

Two scenarios tested: - unaligned stride - Stride too small Signed-off-by: Gabriel Krisman Bertazi --- tests/kms_ccs.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index

[Intel-gfx] [PATCH i-g-t v4 2/6] lib/igt_kms: Fix off-by-one bug on skip of missing pipe

display->n_pipes is zero-indexed, so N returned in igt_display_get_n_pipes is already not a valid pipe. This patch prevents kms_ccs from going nuts when testing the first unxesting pipe. Signed-off-by: Gabriel Krisman Bertazi Reviewed-by: Maarten Lankhorst

[Intel-gfx] [PATCH i-g-t v4 3/6] tests/kms_ccs: Prevent segfault if pipe is not supported

for_each_plane_on_pipe() indexes bad memory when iterating over an invalid pipe. Make sure the pipe exists before trying to use it. This prevents the crash below: root@ideacentre:~# igt-gpu-tools/tests/kms_ccs --r pipe-D-crc-sprite-planes-basic IGT-Version: 1.19-g59f0e3d182a8 (x86_64) (Linux:

[Intel-gfx] [PATCH i-g-t v4 1/6] tests/kms_ccs: Test pipes other than pipe A

Commit d41c4ccbd2f9 ("tests/kms_ccs: Fix subtest enumeration") accidently removed the update of data.pipe, causing kms_ccs to silently only test PIPE_A. This fixes the behavior reported by Daniel Vetter where tests would succeed even on nonexistent pipes. Signed-off-by: Gabriel Krisman Bertazi

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe A

== Series Details == Series: series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe A URL : https://patchwork.freedesktop.org/series/30991/ State : success == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,01/11] drm/i915/execlists: Move request unwinding to a separate function

== Series Details == Series: series starting with [v2,01/11] drm/i915/execlists: Move request unwinding to a separate function URL : https://patchwork.freedesktop.org/series/30983/ State : failure == Summary == Test gem_ctx_param: Subgroup invalid-param-set: pass

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

On 09/27/2017 02:17 PM, Rodrigo Vivi wrote: On Wed, Sep 27, 2017 at 09:08:10PM +, Oscar Mateo wrote: On 09/27/2017 02:01 PM, Rodrigo Vivi wrote: On CNL, HDC_CHICKEN0 "is write-only from LRI command. However, it is readable for context save." So we have no ways to check the coherency by

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

On 09/27/2017 02:01 PM, Rodrigo Vivi wrote: On CNL, HDC_CHICKEN0 "is write-only from LRI command. However, it is readable for context save." So we have no ways to check the coherency by reading it back on our tests. So let's just write that bit directly without saving it to

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

On Wed, Sep 27, 2017 at 09:08:10PM +, Oscar Mateo wrote: > > > On 09/27/2017 02:01 PM, Rodrigo Vivi wrote: > > On CNL, HDC_CHICKEN0 "is write-only from LRI command. > > However, it is readable for context save." > > > > So we have no ways to check the coherency by reading it back on > > our

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow optimized platform checks

== Series Details == Series: drm/i915: Allow optimized platform checks URL : https://patchwork.freedesktop.org/series/30982/ State : success == Summary == Test kms_flip: Subgroup flip-vs-wf_vblank-interruptible: fail -> PASS (shard-hsw) Test perf:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

== Series Details == Series: drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0. URL : https://patchwork.freedesktop.org/series/31001/ State : success == Summary == Series 31001v1 drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

[Intel-gfx] [PATCH v1] drm/i915: Enhanced for initialize partially filled pagetables

if vgpu active, the page table entry should be initialized after allocation and then the hypersivor can ping pages succesuffly, otherwise hypervisor will ping pages failed and the host will print a lot of annoying errors such as “ERROR gvt: guest page write error -22, gfn 0x7ada8, pa 0x7ada89a8,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enhanced for initialize partially filled pagetables

== Series Details == Series: drm/i915: Enhanced for initialize partially filled pagetables URL : https://patchwork.freedesktop.org/series/31029/ State : success == Summary == Series 31029v1 drm/i915: Enhanced for initialize partially filled pagetables

Re: [Intel-gfx] [PATCH] drm/dp: Avoid needless delay while link training

>On Tue, 26 Sep 2017, "Lee, Shawn C" wrote: >> DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (Eh) >> bit7 to indicate Extended Receiver Capability. A DPRX with DPCD Rev. >> 1.4 (or higher) must have an Extended Receiver Capability field. >> Driver have to clear

[Intel-gfx] [PATCH 2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all the host support this feature, need to check the BIT(3) of caps in PVINFO. Signed-off-by: Weinan Li Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_vgpu.c | 5 +

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Here goes the drm/i915 fixes for 4.14-rc3 Couple fixes for stable: - Fix ELD connector types and consequently audio on DP (Jani). - Ignore HDMI on Port A and consequently fix an ops on i915 probe when VBT advertises HDMI on Port A (Jani). And a small fix: - That removes a

[Intel-gfx] [PATCH v2] drm/dp: Do not prune the last mode on the connector

Currently the drm_mode_prune_invalid() function will prune all the modes if it finds that the mode-status is not MODE_OK. But if it ends up pruning all modes then there are no modes left for that connector which will eventually result into a black screen as userspace sees no modes from the kernel.

[Intel-gfx] ✗ Fi.CI.IGT: warning for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev3)

== Series Details == Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev3) URL : https://patchwork.freedesktop.org/series/30860/ State : warning == Summary == Test gem_exec_schedule: Subgroup preempt-contexts-bsd: pass -> SKIP

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/dp: Do not prune the last mode on the connector (rev2)

== Series Details == Series: drm/dp: Do not prune the last mode on the connector (rev2) URL : https://patchwork.freedesktop.org/series/31018/ State : failure == Summary == Series 31018v2 drm/dp: Do not prune the last mode on the connector

[Intel-gfx] [PATCH 1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

The engine provides a mirror of the CSB and CSB write pointer in the HWSP. Read these status from virtual HWSP in VM can reduce CPU utilization while applications have much more short GPU workloads. Here we update the corresponding data in virtual HWSP as it in virtual MMIO. Before read these

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

== Series Details == Series: drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0. URL : https://patchwork.freedesktop.org/series/31001/ State : failure == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

== Series Details == Series: series starting with [1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP URL : https://patchwork.freedesktop.org/series/31033/ State : failure == Summary == Series 31033 revision 1 was fully merged or fully failed: no git log

[Intel-gfx] [PATCH v11 06/11] drm/i915/guc: Make GuC related disable/destroy functions not depend on i915.enable_guc_submission

During GuC load/enable, state is setup by driver that can be looked at while disabling. So remove the check for i915.enable_guc_submission parameter in those functions. Suggested-by: Chris Wilson Signed-off-by: Sagar Arun Kamble Cc: Michal

[Intel-gfx] [PATCH v11 08/11] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume

Apart from configuring interrupts, we need to update the ggtt invalidate interface and GuC communication on suspend/resume. This functionality can be reused for other suspend and reset paths. v2: Rebase w.r.t removal of GuC code restructuring. v3: Removed GuC specific helpers as tasks other than

[Intel-gfx] [PATCH v11 11/11] drm/i915/guc: Fix GuC cleanup in unload path

We ensure that GuC is completely suspended and client is destroyed in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw should just take care of cleanup, hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly we also updated as

[Intel-gfx] [PATCH v11 03/11] drm/i915: Move i915_gem_restore_fences to i915_gem_resume

i915_gem_restore_fences is GEM resumption task hence it is moved to i915_gem_resume from i915_restore_state. Signed-off-by: Sagar Arun Kamble Cc: Chris Wilson Cc: Michal Wajdeczko Cc: Michał Winiarski

[Intel-gfx] [PATCH v11 01/11] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

These changes are preparation to handle GuC suspend/resume. Prepared helper i915_gem_runtime_resume to reinitialize suspended gem setup. Returning status from i915_gem_runtime_suspend and i915_gem_resume. This will be placeholder for handling any errors from uC suspend/resume in upcoming patches.

[Intel-gfx] [PATCH v11 05/11] drm/i915/guc: Introduce intel_uc_sanitize

Currently GPU is reset at the end of suspend via i915_gem_sanitize. On resume, GuC will not be loaded until intel_uc_init_hw happens during GEM resume flow but action to exit sleep can be sent to GuC considering the FW load status. To make sure we don't invoke that action update GuC FW load status

[Intel-gfx] [PATCH v11 10/11] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset

Before i915 reset, we need to disable GuC submission and suspend GuC operations as it is recreated during intel_uc_init_hw. We can't reuse the intel_uc_suspend functionality as reset path already holds struct_mutex. v2: Rebase w.r.t removal of GuC code restructuring. Updated reset_prepare

[Intel-gfx] [PATCH v11 04/11] drm/i915: Create uC runtime and system suspend/resume helpers

Prepared generic helpers intel_uc_suspend, intel_uc_resume, intel_uc_runtime_suspend, intel_uc_runtime_resume. These are called from respective GEM functions. Only exception is intel_uc_resume that needs to be called w/ or w/o GuC loaded in i915_drm_resume path. Changes to add WOPCM condition

[Intel-gfx] [PATCH v11 00/11] GEM/GuC Suspend/Resume/Reset fixes and restructuring

Older series can be found at https://patchwork.freedesktop.org/series/30715/ https://patchwork.freedesktop.org/series/30502/ https://patchwork.freedesktop.org/series/30351/ v1-v8: Part of above three series. v9: Fixed patch 1 based on review inputs from Michal Winiarski. Rebased all patches.

[Intel-gfx] [PATCH v11 07/11] drm/i915/guc: Update i915.enable_guc_loading check in intel_uc_fini_hw

With most of the GuC disabling now separated from enable_guc_submission parameter, only function that needs GuC parameter check is i915_disable_guc_ggtt as that is enabled based on GuC kernel parameters. Hence i915_disable_guc_ggtt is being called when enable_guc_loading is set. Signed-off-by:

[Intel-gfx] [PATCH v11 09/11] drm/i915/guc: Update GuC suspend functionality in intel_uc_suspend

With this patch we disable GuC submission in i915_drm_suspend path. This will destroy the client which will be setup back again. We also reuse the complete sanitization done via intel_uc_runtime_suspend in this path. Post i915_drm_resume, this state is recreated by intel_uc_init_hw hence we need

[Intel-gfx] [PATCH v11 02/11] drm/i915: Update GEM suspend/resume flows with GuC suspend/resume functions

This patch moves GuC suspend/resume handlers to corresponding GEM handlers and orders them properly in the runtime and system suspend/resume flows. v2: Removed documentation of suspend/resume handlers as those are not interfaces and are just hooks. (Chris) v3: Rebase. Removed

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,01/11] drm/i915/execlists: Move request unwinding to a separate function

== Series Details == Series: series starting with [v2,01/11] drm/i915/execlists: Move request unwinding to a separate function URL : https://patchwork.freedesktop.org/series/30983/ State : success == Summary == Series 30983v1 series starting with [v2,01/11] drm/i915/execlists: Move request

[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/igt_kms: Convert properties to be more atomic-like. (rev2)

== Series Details == Series: lib/igt_kms: Convert properties to be more atomic-like. (rev2) URL : https://patchwork.freedesktop.org/series/30903/ State : failure == Summary == Test pm_rpm: Subgroup modeset-lpsp: pass -> SKIP (shard-hsw) Subgroup

[Intel-gfx] [PATCH] drm/i915: Also discard second CRC on gen8+ platforms.

One of the differences I spotted for GEN8+ platforms when compared to older platforms is that spec for BDW+ includes this sentence: "The first CRC done indication after CRC is first enabled is from only a partial frame, so it will not have the expected CRC result." This is an indication that on

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Also discard second CRC on gen8+ platforms.

== Series Details == Series: drm/i915: Also discard second CRC on gen8+ platforms. URL : https://patchwork.freedesktop.org/series/31023/ State : success == Summary == Series 31023v1 drm/i915: Also discard second CRC on gen8+ platforms.

[Intel-gfx] [PATCH i-g-t] Fix compilation on some distros

Some distros (such as Gentoo) are removing the include of sys/sysmacros.h from sys/types.h. Explicitly include sysmacros.h in files where we use the minor() and major() functions. Signed-off-by: James Ausmus --- lib/igt_debugfs.c | 1 + lib/igt_sysfs.c | 1 +

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe A

== Series Details == Series: series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe A URL : https://patchwork.freedesktop.org/series/30991/ State : failure == Summary == Test kms_flip: Subgroup blt-flip-vs-panning: skip -> PASS (shard-hsw)

[Intel-gfx] [PATCH] drm/dp: Do not prune the last mode on the connector

Currently the drm_mode_prune_invalid() function will prune all the modes if it finds that the mode-status is not MODE_OK. But if it ends up pruning all modes then there are no modes left for that connector which will eventually result into a black screen as userspace sees no modes from the kernel.

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