Re: [Intel-gfx] [PATCH] drm/i915: Remove pre-production pooled-EU w/a for Broxton

Quoting Jani Nikula (2017-11-17 07:44:08) > On Thu, 16 Nov 2017, Rodrigo Vivi wrote: > > On Thu, Nov 16, 2017 at 09:22:23AM +, Jani Nikula wrote: > >> On Wed, 15 Nov 2017, Chris Wilson wrote: > >> > Quoting David Weinehall (2017-11-15

Re: [Intel-gfx] [PATCH] drm/i915: Add might_sleep() check to wait_for()

Quoting Tvrtko Ursulin (2017-11-15 09:11:13) > > On 14/11/2017 21:56, Chris Wilson wrote: > > We should long past the time of trying to use wait_for() from inside > > atomic contexts, so add a might_sleep() check to prevent misuse. > > > > Signed-off-by: Chris Wilson >

Re: [Intel-gfx] [PATCH 06/10] drm/edid: Fix cea mode aspect ratio handling

Regards Shashank On 11/17/2017 5:05 PM, Ville Syrjälä wrote: On Fri, Nov 17, 2017 at 08:49:49AM +0530, Sharma, Shashank wrote: Regards Shashank On 11/16/2017 9:53 PM, Ville Syrjälä wrote: On Thu, Nov 16, 2017 at 08:21:44PM +0530, Sharma, Shashank wrote: Regards Shashank On 11/13/2017

Re: [Intel-gfx] [PATCH] drm/i915: Remove pre-production pooled-EU w/a for Broxton

On Fri, 17 Nov 2017, Chris Wilson wrote: > That seems like a reasonably policy. > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 57dfaf04d819..0be79cf993fa 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

Quoting Lionel Landwerlin (2017-11-17 11:08:07) > On 17/11/17 10:53, Chris Wilson wrote: > > Is this subslicing only for the render unit; are all platforms going to > > have the same fusing across all units? At the least, I thought we would > > be able to configure the powergating of the different

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add a policy note for removing workarounds

== Series Details == Series: drm/i915: Add a policy note for removing workarounds URL : https://patchwork.freedesktop.org/series/33995/ State : success == Summary == Series 33995v1 drm/i915: Add a policy note for removing workarounds

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

Quoting Lionel Landwerlin (2017-11-16 16:00:03) > With the introduction of asymetric slices in CNL, we cannot rely on > the previous SUBSLICE_MASK getparam. Here we introduce a more detailed > way of querying the Gen's GPU topology that doesn't aggregate numbers. > > This is essential for

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

Cc: Greg On Wed, 15 Nov 2017, Ville Syrjälä wrote: > On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.le...@verizon.com wrote: >> On Wed, Nov 15, 2017 at 01:08:05PM +0200, Ville Syrjälä wrote: >> >On Wed, Nov 15, 2017 at 02:45:43AM +,

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

On 17/11/17 11:17, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-11-17 11:08:07) On 17/11/17 10:53, Chris Wilson wrote: Is this subslicing only for the render unit; are all platforms going to have the same fusing across all units? At the least, I thought we would be able to configure the

Re: [Intel-gfx] [PATCH 07/10] drm/edid: Don't send bogus aspect ratios in AVI infoframes

On Fri, Nov 17, 2017 at 08:53:54AM +0530, Sharma, Shashank wrote: > Regards > > Shashank > > > On 11/16/2017 9:56 PM, Ville Syrjälä wrote: > > On Thu, Nov 16, 2017 at 08:31:36PM +0530, Sharma, Shashank wrote: > >> Regards > >> > >> Shashank > >> > >> > >> On 11/13/2017 10:34 PM, Ville Syrjala

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure

Quoting Patchwork (2017-11-17 11:56:31) > == Series Details == > > Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure > URL : https://patchwork.freedesktop.org/series/33994/ > State : success > > == Logs == > > For more details see: >

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2)

== Series Details == Series: drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2) URL : https://patchwork.freedesktop.org/series/33608/ State : warning == Summary == Test kms_flip: Subgroup plain-flip-fb-recreate-interruptible: fail -> PASS (shard-hsw)

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

On 16/11/2017 16:00, Lionel Landwerlin wrote: With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

On 17/11/17 09:37, Tvrtko Ursulin wrote: On 16/11/2017 16:00, Lionel Landwerlin wrote: With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate

Re: [Intel-gfx] [PATCH] drm/i915: Mark the userptr invalidate workqueue as WQ_MEM_RECLAIM

Quoting Matthew Auld (2017-11-17 10:56:54) > On 14 November 2017 at 17:35, Chris Wilson wrote: > > Commit 21cc6431e0c2 ("drm/i915: Mark the userptr invalidate workqueue > > as WQ_MEM_RECLAIM") tried to fixup the check_flush_dependency warning > > for hitting

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure

== Series Details == Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure URL : https://patchwork.freedesktop.org/series/33994/ State : success == Summary == Test kms_busy: Subgroup extended-modeset-hang-newfb-with-reset-render-a: skip ->

[Intel-gfx] [CI] drm/i915: Automatic i915_switch_context for legacy

During request construction, after pinning the context we know whether or not we have to emit a context switch. So move this common operation from every caller into i915_gem_request_alloc() itself. v2: Always submit the request if we emitted some commands during request construction, as typically

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

On Fri, Nov 17, 2017 at 02:53:43PM +0200, Ville Syrjälä wrote: > On Fri, Nov 17, 2017 at 01:41:23PM +0100, Greg KH wrote: > > On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote: > > > > > > Cc: Greg > > > > > > On Wed, 15 Nov 2017, Ville Syrjälä wrote: >

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

On Fri, 17 Nov 2017, Greg KH wrote: > On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote: >> >> Cc: Greg >> >> On Wed, 15 Nov 2017, Ville Syrjälä wrote: >> > On Wed, Nov 15, 2017 at 04:44:54PM +,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2)

== Series Details == Series: drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2) URL : https://patchwork.freedesktop.org/series/33608/ State : success == Summary == Series 33608v2 drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+

[Intel-gfx] [PATCH] drm/i915: Add a policy note for removing workarounds

Rodrigo gave a persuasive argument for keeping workarounds: that they serve as a good guide for the bring up of the next generation. Not only do workarounds persist into the early revisions, they show where the workarounds were previously added to the code flow and sometimes the old workarounds

Re: [Intel-gfx] [PATCH v5 1/2] drm/i915/selftests: Add a GuC doorbells selftest

Quoting Michel Thierry (2017-11-16 22:06:31) > The first test aims to check guc_init_doorbell_hw, changing the existing > guc clients and doorbells state before calling it. > > The second test tries to create as many clients as it is currently possible > (currently limited to max number of

Re: [Intel-gfx] [PATCH 06/10] drm/edid: Fix cea mode aspect ratio handling

On Fri, Nov 17, 2017 at 08:49:49AM +0530, Sharma, Shashank wrote: > Regards > > Shashank > > > On 11/16/2017 9:53 PM, Ville Syrjälä wrote: > > On Thu, Nov 16, 2017 at 08:21:44PM +0530, Sharma, Shashank wrote: > >> Regards > >> > >> Shashank > >> > >> > >> On 11/13/2017 10:34 PM, Ville Syrjala

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation

On Thu, Nov 16, 2017 at 09:01:03PM +, Chris Wilson wrote: > Quoting Ville Syrjala (2017-11-16 19:14:50) > > From: Ville Syrjälä > > > > Currently we're pinning the fence for the rotated GTT view. That doesn't > > acually make any sense since the fence is used

Re: [Intel-gfx] [PATCH 4/4] drm/i915: expose engine availability through sysfs

On 16/11/2017 16:00, Lionel Landwerlin wrote: This enables userspace to discover the engines available on the GPU. Here is the layout : /sys/devices/pci:00/:00:02.0/drm/card0/engines ├── bcs0 │   ├── class │   └── instance ├── rcs0 │   ├── class │   └── instance ├── vcs0 │   ├── class

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

On 17/11/17 10:53, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-11-16 16:00:03) With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

On Fri, Nov 17, 2017 at 01:41:23PM +0100, Greg KH wrote: > On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote: > > > > Cc: Greg > > > > On Wed, 15 Nov 2017, Ville Syrjälä wrote: > > > On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.le...@verizon.com

Re: [Intel-gfx] [PATCH 4/4] drm/i915: expose engine availability through sysfs

On 17/11/17 09:51, Tvrtko Ursulin wrote: On 16/11/2017 16:00, Lionel Landwerlin wrote: This enables userspace to discover the engines available on the GPU. Here is the layout : /sys/devices/pci:00/:00:02.0/drm/card0/engines ├── bcs0 │   ├── class │   └── instance ├── rcs0 │   ├──

Re: [Intel-gfx] [PATCH v3 08/11] drm/i915: Pass crtc_state to ips toggle functions, v2

Op 13-11-17 om 18:18 schreef Ville Syrjälä: > On Fri, Nov 10, 2017 at 12:35:00PM +0100, Maarten Lankhorst wrote: >> Changes since v1: >> - Only pass crtc_state, not crtc. >> >> Signed-off-by: Maarten Lankhorst > Reviewed-by: Ville Syrjälä

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add a policy note for removing workarounds

== Series Details == Series: drm/i915: Add a policy note for removing workarounds URL : https://patchwork.freedesktop.org/series/33995/ State : success == Summary == Test kms_cursor_legacy: Subgroup flip-vs-cursor-varying-size: fail -> PASS (shard-hsw)

Re: [Intel-gfx] [PATCH 06/10] drm/edid: Fix cea mode aspect ratio handling

On Fri, Nov 17, 2017 at 05:50:11PM +0530, Sharma, Shashank wrote: > Regards > > Shashank > > > On 11/17/2017 5:05 PM, Ville Syrjälä wrote: > > On Fri, Nov 17, 2017 at 08:49:49AM +0530, Sharma, Shashank wrote: > >> Regards > >> > >> Shashank > >> > >> > >> On 11/16/2017 9:53 PM, Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915: Enable runtime pm

On Thu, Nov 16, 2017 at 08:24:02PM +0200, David Weinehall wrote: > On Wed, Nov 08, 2017 at 04:25:42PM +0200, David Weinehall wrote: > > On Tue, Nov 07, 2017 at 05:18:21PM +0100, Daniel Vetter wrote: > > > Now that we have CI, and that pm_rpm fully passes (I guess the audio > > > folks have

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure

== Series Details == Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure URL : https://patchwork.freedesktop.org/series/33994/ State : success == Summary == Series 33994v1 drm/i915/selftests: Report ENOMEM clearly for an allocation failure

Re: [Intel-gfx] [PATCH] drm/i915: Add a policy note for removing workarounds

On Fri, 17 Nov 2017, Chris Wilson wrote: > Rodrigo gave a persuasive argument for keeping workarounds: that they > serve as a good guide for the bring up of the next generation. Not only > do workarounds persist into the early revisions, they show where the > workarounds

[Intel-gfx] [PATCH] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

If we can not run the drunk_hole test because we couldn't allocate the memory for the permutation array (even after we tried trimming the size), report a clear ENOMEM. Similary, if we are asked to operate on a hole too small for ourselves, make it skip quietly. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Mark the userptr invalidate workqueue as WQ_MEM_RECLAIM

On 14 November 2017 at 17:35, Chris Wilson wrote: > Commit 21cc6431e0c2 ("drm/i915: Mark the userptr invalidate workqueue > as WQ_MEM_RECLAIM") tried to fixup the check_flush_dependency warning > for hitting i915_gem_userptr_mn_invalidate_range_start from within the >

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

On 17 November 2017 at 10:17, Chris Wilson wrote: > If we can not run the drunk_hole test because we couldn't allocate the > memory for the permutation array (even after we tried trimming the > size), report a clear ENOMEM. Similary, if we are asked to operate on a >

[Intel-gfx] [PATCH v2 (resend) 2/6] drm/i915: Program gen3- watermarks atomically

With the atomic watermark calculations calculate intermediary watermark values and update the watermarks atomically. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/intel_drv.h | 5 +-

[Intel-gfx] [PATCH v2 (resend) 0/6] drm/i915: Calculate watermarks for gen4 and lower atomically.

It's time to kill off the legacy watermark infrastructure. Convert the existing watermark calculations to atomic, and remove the legacy ones. Resend, only rebased.. Maarten Lankhorst (6): drm/i915: Calculate gen3- watermarks semi-atomically, v3. drm/i915: Program gen3- watermarks atomically

[Intel-gfx] [PATCH v2 (resend) 3/6] drm/i915: Calculate gen4 watermarks semiatomically.

Gen4 watermark is handled same as gen3-. Calculate the optimal watermarks atomically first, and program it in the legacy helper. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_pm.c | 141 1 file

[Intel-gfx] [PATCH v2 (resend) 5/6] drm/i915: Kill off intel_crtc_active.

Use crtc->active directly instead. This is still not completely optimal and needs fixing, but it's about as good as using intel_crtc_active. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 19 ---

[Intel-gfx] [PATCH v2 (resend) 4/6] drm/i915: Program gen4 watermarks atomically

We're already calculating the watermarks correctly, now we have to program them too. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_pm.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Automatic i915_switch_context for legacy

Chris Wilson writes: > Quoting Mika Kuoppala (2017-11-16 14:00:13) >> Chris Wilson writes: >> >> > During request construction, after pinning the context we know whether >> > or not we have to emit a context switch. So move this common

[Intel-gfx] [PATCH v2 (resend) 6/6] drm/i915: Rip out legacy watermark infrastructure, v2.

The legacy watermark infrastructure is now unused, so remove it. Changes since v1: - Rebase on top of legacy_cursor_update fix. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_atomic.c | 2 -

[Intel-gfx] [PATCH v2 (resend) 1/6] drm/i915: Calculate gen3- watermarks semi-atomically, v3.

The gen3 watermark calculations are converted to atomic, but the wm update calls are still done through the legacy functions. This will make it easier to bisect things if they go wrong. CI was having issues on the kms_cursor_legacy tests with too much debug info printed out, in order to reduce

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote: > > Cc: Greg > > On Wed, 15 Nov 2017, Ville Syrjälä wrote: > > On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.le...@verizon.com wrote: > >> On Wed, Nov 15, 2017 at 01:08:05PM +0200, Ville Syrjälä

[Intel-gfx] [CI 1/2] drm/i915: Automatic i915_switch_context for legacy

During request construction, after pinning the context we know whether or not we have to emit a context switch. So move this common operation from every caller into i915_gem_request_alloc() itself. v2: Always submit the request if we emitted some commands during request construction, as typically

Re: [Intel-gfx] [PATCH v5 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

On Thu, Nov 16, 2017 at 03:21:32PM -0800, James Ausmus wrote: > On Mon, Oct 23, 2017 at 05:50:32PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Rename enum plane to enum i9xx_plane_id to make it clear that it only > > applies to pre-SKL platforms. >

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

On Fri, Nov 17, 2017 at 03:01:08PM +0200, Jani Nikula wrote: > On Fri, 17 Nov 2017, Greg KH wrote: > > On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote: > >> > >> Cc: Greg > >> > >> On Wed, 15 Nov 2017, Ville Syrjälä wrote:

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Automatic i915_switch_context for legacy

== Series Details == Series: series starting with [CI,1/2] drm/i915: Automatic i915_switch_context for legacy URL : https://patchwork.freedesktop.org/series/34005/ State : failure == Summary == Series 34005v1 series starting with [CI,1/2] drm/i915: Automatic i915_switch_context for legacy

[Intel-gfx] [CI] drm/i915: Pull the unconditional GPU cache invalidation into request construction

As the request now may implicitly invoke a context-switch, we should follow that with a GPU TLB invalidation. Also even before using GGTT, we should invalidate the TLBs for any updates (as well as the ppgtt invalidates that are unconditionally applied by execbuf). Since we almost always require

[Intel-gfx] [PATCH] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

If we can not run the drunk_hole test because we couldn't allocate the memory for the permutation array (even after we tried trimming the size), report a clear ENOMEM. Similary, if we are asked to operate on a hole too small for ourselves, make it skip quietly. v2: Avoid malloc(0) since that

[Intel-gfx] [PATCH 0/3] drm/i915: Enable fastboot, v2!

Small fixes for IPS, and then we flip the switch! :-) Maarten Lankhorst (3): drm/i915: Make ips_enabled a property depending on whether IPS is enabled. drm/i915: Enable IPS for sprite plane drm/i915: Re-enable fastboot by default drivers/gpu/drm/i915/i915_params.h| 2 +-

[Intel-gfx] [PATCH 1/3] drm/i915: Make ips_enabled a property depending on whether IPS is enabled.

ips_enabled was used as a variable of whether IPS can be enabled or not, but should be used to test whether IPS is actually enabled. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 75 ---

[Intel-gfx] [(resend) PATCH 3/3] drm/i915: Re-enable fastboot by default

This fix was originally reverted because it left a chromebook pixel black, and no immediate fix was available. This has been fixed in the meantime. Rather than trying to remove the parameter, set it to default to true for now, so we can always back out if required. Signed-off-by: Maarten

[Intel-gfx] [PATCH 2/3] drm/i915: Enable IPS for sprite plane

Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

Re: [Intel-gfx] [PATCH v2] drm/i915: Initialise entry in intel_ppat_get() for older compilers

Thanks! Looks good to me. -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Wednesday, November 15, 2017 3:17 PM To: intel-gfx@lists.freedesktop.org Cc: Chris Wilson ; Joonas Lahtinen ; Wang, Zhi A

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expose more GPU properties through sysfs (rev2)

== Series Details == Series: drm/i915: Expose more GPU properties through sysfs (rev2) URL : https://patchwork.freedesktop.org/series/33950/ State : success == Summary == Series 33950v2 drm/i915: Expose more GPU properties through sysfs

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Make ips_enabled a property depending on whether IPS is enabled.

On Fri, Nov 17, 2017 at 04:37:54PM +0100, Maarten Lankhorst wrote: > ips_enabled was used as a variable of whether IPS can be enabled or not, > but should be used to test whether IPS is actually enabled. > > Signed-off-by: Maarten Lankhorst > --- >

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Pull the unconditional GPU cache invalidation into request construction

== Series Details == Series: drm/i915: Pull the unconditional GPU cache invalidation into request construction URL : https://patchwork.freedesktop.org/series/34007/ State : failure == Summary == Series 34007v1 drm/i915: Pull the unconditional GPU cache invalidation into request construction

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Enable IPS for sprite plane

On Fri, Nov 17, 2017 at 04:37:55PM +0100, Maarten Lankhorst wrote: > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/intel_display.c | 13 ++--- > 1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git

Re: [Intel-gfx] [PATCH 1/1] drm/i915/cnl: Extend HDMI 2.0 support to CNL.

On Wed, 15 Nov 2017, David Weinehall wrote: > On Mon, Nov 13, 2017 at 10:47:44AM -0800, Rodrigo Vivi wrote: >> On Sat, Nov 11, 2017 at 09:43:44AM +, Sharma, Shashank wrote: >> > Regards >> > >> > Shashank >> > >> > >> > On 11/11/2017 3:56 AM, Rodrigo Vivi

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Always pin the fence for scanout on gen2/3 and primary planes

On Thu, Nov 16, 2017 at 12:49:23PM -0800, Rodrigo Vivi wrote: > On Thu, Nov 16, 2017 at 07:14:47PM +, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > The current code is trying to be lazy with fences on scanout buffers. > > That looks broken for several

Re: [Intel-gfx] [(resend) PATCH 1/2] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.

On Fri, Nov 17, 2017 at 03:47:58PM +0100, Maarten Lankhorst wrote: > Op 17-11-17 om 14:31 schreef Ville Syrjälä: > > On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote: > >> The watermarks it should calculate against are the old optimal watermarks. > >> The currently active crtc

[Intel-gfx] [PATCH v2 2/4] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

Now that we have that information in topology fields, let's just reused it. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_debugfs.c | 26 ++ 1 file changed, 10 insertions(+), 16 deletions(-) diff --git

[Intel-gfx] [PATCH v2 0/4] drm/i915: Expose more GPU properties through sysfs

Hi, An update based on Chris & Tvrtko's feedback. Cheers, Lionel Landwerlin (4): drm/i915: store all subslice masks drm/i915/debugfs: reuse max slice/subslices already stored in sseu drm/i915: expose engine availability through sysfs drm/i915: expose EU topology through sysfs

[Intel-gfx] [PATCH v2 1/4] drm/i915: store all subslice masks

Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymetric (for example slice0 has different number of subslices as slice1+). This change stores all subslices masks for all slices rather than having a single mask that applies to all

[Intel-gfx] [PATCH v2 4/4] drm/i915: expose EU topology through sysfs

With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts of the GPU with the OA unit, because signals

[Intel-gfx] [PATCH v2 3/4] drm/i915: expose engine availability through sysfs

This enables userspace to discover the engines available on the GPU. Here is the layout on a Skylake GT4: /sys/devices/pci:00/:00:02.0/drm/card0/gt ├── bcs │   └── 0 │   ├── capabilities │   ├── class │   └── id ├── rcs │   └── 0 │   ├── capabilities │   ├── class │  

Re: [Intel-gfx] [(resend) PATCH 1/2] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.

On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote: > The watermarks it should calculate against are the old optimal watermarks. > The currently active crtc watermarks are pure fiction, and are invalid in > case of a nonblocking modeset, page flip enabling/disabling planes or any >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Automatic i915_switch_context for legacy

== Series Details == Series: drm/i915: Automatic i915_switch_context for legacy URL : https://patchwork.freedesktop.org/series/34002/ State : success == Summary == Series 34002v1 drm/i915: Automatic i915_switch_context for legacy

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

On Fri, Nov 17, 2017 at 01:13:27PM +, Emil Velikov wrote: > Hi Greg, all, > > Pardon for the silly question, but I'm struggling to find > documentation about this new 'autoselection' process? > Where can one read up on it - be that about the tooling or the heuristics > used? > > I think the

[Intel-gfx] [CI 1/2] drm/i915: Pull the unconditional GPU cache invalidation into request construction

As the request now may implicitly invoke a context-switch, we should follow that with a GPU TLB invalidation. Also even before using GGTT, we should invalidate the TLBs for any updates (as well as the ppgtt invalidates that are unconditionally applied by execbuf). Since we almost always require

[Intel-gfx] [CI 2/2] drm/i915: Automatic i915_switch_context for legacy

During request construction, after pinning the context we know whether or not we have to emit a context switch. So move this common operation from every caller into i915_gem_request_alloc() itself. v2: Always submit the request if we emitted some commands during request construction, as typically

Re: [Intel-gfx] [PATCH AUTOSEL for 4.9 36/56] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

Hi Greg, all, Pardon for the silly question, but I'm struggling to find documentation about this new 'autoselection' process? Where can one read up on it - be that about the tooling or the heuristics used? I think the above may be the core reason behind the discussion here. Thanks Emil

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Remove obsolete ringbuffer emission for gen8+

Chris Wilson writes: > Since removing the module parameter to force selection of ringbuffer > emission for gen8, the code is defunct. Remove it. > > To put the difference into perspective, a couple of microbenchmarks > (bdw i7-5557u, 20170324): >

Re: [Intel-gfx] [PATCH igt] lib/i915: Prepare for the loss of i915.enable_execlists parameter

Chris Wilson writes: > If we can't find the enable_execlists parameter, presume that the switch > is forced by the kernel and enabled for all hw supporting execlists. We > don't have a GETPARAM or ENGINE_INFO to query the internal details. > > Signed-off-by: Chris

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Report ENOMEM clearly for an allocation failure

On 17 November 2017 at 15:31, Chris Wilson wrote: > If we can not run the drunk_hole test because we couldn't allocate the > memory for the permutation array (even after we tried trimming the > size), report a clear ENOMEM. Similary, if we are asked to operate on a >

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Calculate watermarks for gen4 and lower atomically.

== Series Details == Series: drm/i915: Calculate watermarks for gen4 and lower atomically. URL : https://patchwork.freedesktop.org/series/34001/ State : failure == Summary == Applying: drm/i915: Calculate gen3- watermarks semi-atomically, v3. Applying: drm/i915: Program gen3- watermarks

Re: [Intel-gfx] [PATCH v3 4/4] drm/i915: Add is-wedged flag to intel_engine_dump()

Chris Wilson writes: > Comparing the state tested by intel_engine_is_idle() and printed by > intel_engine_dump(), the only bit not shown is whether or not the device > is wedged. Add that little bit of information to the pretty printer so > that if the engine fails to

[Intel-gfx] [RFC 2/2] drm/i915/pmu: Allow fine-grained PMU access control

From: Tvrtko Ursulin We implement the new pmu->is_privileged callback and add our own sysctl as /proc/sys/dev/i915/pmu_stream_paranoid (defaulting to true), which enables system administrators to override the global /proc/sys/kernel/perf_event_paranoid setting for i915

[Intel-gfx] [RFC 1/2] perf/pmu: Allow PMU providers to override system-wide security settings

From: Tvrtko Ursulin To allow system administrators finer-grained control over security settings, we add an optional pmu->is_privileged(pmu, event) callback which is consulted when unprivileged system-wide uncore event collection is disabled. Signed-off-by: Tvrtko

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Automatic i915_switch_context for legacy

== Series Details == Series: drm/i915: Automatic i915_switch_context for legacy URL : https://patchwork.freedesktop.org/series/34002/ State : failure == Summary == Test gem_exec_reloc: Subgroup basic-range: pass -> INCOMPLETE (shard-snb) Subgroup

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev3)

Quoting Patchwork (2017-11-17 18:37:16) > == Series Details == > > Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure > (rev3) > URL : https://patchwork.freedesktop.org/series/33994/ > State : success > > == Logs == > > For more details see: >

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Runtime disable for eDP DRRS

On Tue, Nov 07, 2017 at 06:38:23PM +, Ramalingam C wrote: > From: "C, Ramalingam" > > Debugfs called i915_drrs_ctl is added to enable and disable the > eDP DRRS. Writing 0 will disable the feature, whereas non-zero > will enable the feature. > > Possibility of

[Intel-gfx] [PATCH v6 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

From: Ville Syrjälä Rename enum plane to enum i9xx_plane_id to make it clear that it only applies to pre-SKL platforms. enum i9xx_plane_id is a global identifier, whereas enum plane_id is per-pipe. We need the old global identifier to index the primary plane (and

[Intel-gfx] [PATCH v3 08/10] drm/i915: Nuke crtc->plane

From: Ville Syrjälä Eliminate crtc->plane since it's pretty much a layering violation. We can always get the plane via crtc->primary if we actually need it. The only ugly thing left is plane_to_crtc_mapping[], but that's still needed by the pre-g4x watermark code.

[Intel-gfx] [PATCH v3 04/10] drm/i915: Use enum i9xx_plane_id for the .get_fifo_size() hooks

From: Ville Syrjälä Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code. v2: s/old_plane_id/i9xx_plane_id/ (Daniel) v3: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Daniel Vetter

[Intel-gfx] [PATCH v4 01/10] drm/i915: Add .get_hw_state() method for planes

From: Ville Syrjälä Add a .get_hw_state() method for planes, returning true or false depending on whether the plane is enabled. Use it to rewrite the plane enabled/disabled asserts in platform agnostic fashion. We do lose the pre-gen4 plane<->pipe mapping checks,

[Intel-gfx] [PATCH v3 09/10] drm/i915: Use plane->get_hw_state() for initial plane fb readout

From: Ville Syrjälä Since we now have a ->get_hw_state() method for planes, let's use that during the initial plane fb readout. v2: s/plane/i9xx_plane/ etc. (James) Cc: James Ausmus Cc: Daniel Vetter Suggested-by:

[Intel-gfx] [PATCH v2 06/10] drm/i915: Nuke ironlake_get_initial_plane_config()

From: Ville Syrjälä The only relevant difference between i9xx_get_initial_plane_config() and ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling. Add that to i9xx_get_initial_plane_config() and nuke ironlake_get_initial_plane_config(). v2:

[Intel-gfx] [PATCH v5 05/10] drm/i915: Cleanup enum pipe/enum plane_id/enum i9xx_plane_id in initial fb readout

From: Ville Syrjälä Use enum pipe, enum plane_id, and enum i9xx_plane_id consistently in the initial framebuffe readout. v2: Use old_plane_id in the ilk code v3: s/old_plane_id/i9xx_plane_id/ (Daniel) v4: Rebase due to GLK/CNL PLANE_COLOR_CTL alpha stuff v5:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev2)

== Series Details == Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev2) URL : https://patchwork.freedesktop.org/series/33994/ State : success == Summary == Test kms_busy: Subgroup extended-modeset-hang-newfb-with-reset-render-a: skip

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Always pin the fence for scanout on gen2/3 and primary planes

On Fri, Nov 17, 2017 at 01:21:35PM +, Ville Syrjälä wrote: > On Thu, Nov 16, 2017 at 12:49:23PM -0800, Rodrigo Vivi wrote: > > On Thu, Nov 16, 2017 at 07:14:47PM +, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > The current code is trying to be

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2)

== Series Details == Series: drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2) URL : https://patchwork.freedesktop.org/series/33608/ State : success == Summary == Series 33608v2 drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane assert/readout cleanups etc. (rev9)

== Series Details == Series: drm/i915: Plane assert/readout cleanups etc. (rev9) URL : https://patchwork.freedesktop.org/series/31758/ State : success == Summary == Series 31758v9 drm/i915: Plane assert/readout cleanups etc.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev3)

== Series Details == Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure (rev3) URL : https://patchwork.freedesktop.org/series/33994/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-shrfb-pgflip-blt: pass

Re: [Intel-gfx] [PATCH v2 2/2] i915/drrs/debugfs: crtc id and psr status

On Tue, Nov 07, 2017 at 06:40:08PM +, Ramalingam C wrote: > From: "C, Ramalingam" > > Existing debugfs entry i915_drrs_status is updated with crtc id and > if PSR is cause for DRRS disabled state. > > [v2]: Dropped the module parameter details as ctl moved from

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix init_clock_gating for resume (rev2)

== Series Details == Series: drm/i915: Fix init_clock_gating for resume (rev2) URL : https://patchwork.freedesktop.org/series/33718/ State : success == Summary == Series 33718v2 drm/i915: Fix init_clock_gating for resume https://patchwork.freedesktop.org/api/1.0/series/33718/revisions/2/mbox/

[Intel-gfx] [PATCH v3 00/10] drm/i915: Plane assert/readout cleanups etc.

From: Ville Syrjälä OK, one more time. This time with s/plane/i9xx_plane/ etc. all over. Maybe that will make everyone happy? Unlikely, but let's try. Patch 3 is the only one missing r-b. Ville Syrjälä (10): drm/i915: Add .get_hw_state() method for planes

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