[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace

== Series Details == Series: drm/i915: expose RCS topology to userspace URL : https://patchwork.freedesktop.org/series/36874/ State : success == Summary == Series 36874v1 drm/i915: expose RCS topology to userspace https://patchwork.freedesktop.org/api/1.0/series/36874/revisions/1/mbox/ Test

[Intel-gfx] [PATCH igt v2] tests: Add a random load generator

Apply a random load to one or all engines in order to apply stress to RPS as it tries to constantly adjust the GPU frequency to meet the changing workload. Signed-off-by: Chris Wilson --- tests/Makefile.sources | 1 + tests/gem_exec_load.c | 178

[Intel-gfx] [PATCH 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

This patch fixes lockdep issue due to circular locking dependency of struct_mutex, i_mutex_key, mmap_sem, relay_channels_mutex. For GuC log relay channel we create debugfs file that requires i_mutex_key lock and we are doing that under struct_mutex. So we introduced newer dependency as:

[Intel-gfx] [PATCH 3/4] drm/i915/guc: Enable interrupts before resuming GuC during runtime resume

GuC log streaming needs interrupts enabled prior to GuC resume but runtime pm interrupt setup was happening post GuC resume. Fix it. While at it, fix the unwinding of steps in the runtime suspend path. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104695 Signed-off-by: Sagar Arun Kamble

[Intel-gfx] [PATCH 2/4] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

Disabling GuC interrupts involves access to GuC IRQ control registers hence ensure device is RPM awake. v2: Add comment about need to synchronize flush work and log runtime destroy v3: Moved patch earlier in the series and removed comment about future work. (Tvrtko) v4-v5: Rebase.

[Intel-gfx] [PATCH v11 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

Now that we have that information in topology fields, let's just reused it. v2: Style tweaks (Tvrtko) Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 27 +++

[Intel-gfx] [PATCH v11 4/6] drm/i915: add rcs topology to error state

This might be useful information for developers looking at an error state. v2: Place topology towards the end of the error state (Chris) v3: Reuse common printing code (Michal) v4: Make this a one-liner (Chris) Signed-off-by: Lionel Landwerlin Reviewed-by:

[Intel-gfx] [PATCH 4/4] [HAX] Revert "drm/i915/guc: Keep GuC log disabled by default"

Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be running. This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5. --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_guc_log.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Check reserve_memtype for failure

== Series Details == Series: drm/i915: Check reserve_memtype for failure URL : https://patchwork.freedesktop.org/series/36854/ State : warning == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-render: fail -> PASS

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

I recommend that this is tested with a HACK to enable the GUC logs again, so that we can see if it really fixes the issue. > -Original Message- > From: Kamble, Sagar A > Sent: Monday, January 22, 2018 10:26 AM > To: intel-gfx@lists.freedesktop.org > Cc: Kamble, Sagar A

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

On 1/22/2018 1:54 PM, Lofstedt, Marta wrote: I recommend that this is tested with a HACK to enable the GUC logs again, so that we can see if it really fixes the issue. Yes. Patch 4 in the series enables the GuC log for testing. -Original Message- From: Kamble, Sagar A Sent: Monday,

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Protect WC stash allocation against direct reclaim

== Series Details == Series: drm/i915: Protect WC stash allocation against direct reclaim URL : https://patchwork.freedesktop.org/series/36855/ State : success == Summary == Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

== Series Details == Series: series starting with [1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex URL : https://patchwork.freedesktop.org/series/36875/ State : success == Summary == Series 36875v1 series starting with [1/4] drm/i915/guc: Fix lockdep due

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

On 1/22/2018 3:46 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-01-22 08:26:01) +int intel_guc_log_relay_create(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + struct rchan *guc_log_relay_chan; + size_t n_subbufs, subbuf_size; +

Re: [Intel-gfx] [PATCH i-g-t 4/4] scripts/trace.pl: Simplify 'end' & 'notify' generation

On 20/01/2018 00:24, john.c.harri...@intel.com wrote: From: John Harrison Delay the auto-generation of end/notify values until the point where everything is known. As opposed to potentially generating them multiple times with differing values. Signed-off-by: John

Re: [Intel-gfx] [PATCH] drm/i915: Protect WC stash allocation against direct reclaim

Quoting Matthew Auld (2018-01-22 11:04:33) > On 21 January 2018 at 17:31, Chris Wilson wrote: > > As we attempt to allocate pages for use in a new WC stash, direct > > reclaim may run underneath us and fill up the WC stash. We have to be > > careful then not to overflow

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Expose per-engine client busyness

On 19/01/2018 13:45, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Expose per-client and per-engine busyness under the previously added sysfs client root. The new file is named 'busy' and contains a list of, one line for each engine, monotonically increasing

[Intel-gfx] [PATCH v2] drm/i915/execlists: Skip forcewake for ELSP submission

Now that we can read the CSB from the HWSP, we may avoid having to perform mmio reads entirely and so forgo the rigmarole of the forcewake dance. v2: Include forcewake hint for GEM_TRACE readback of mmio. If we don't hold fw ourselves, the reads may return garbage. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

Quoting Sagar Arun Kamble (2018-01-22 08:26:02) > Disabling GuC interrupts involves access to GuC IRQ control registers > hence ensure device is RPM awake. > > v2: Add comment about need to synchronize flush work and log runtime > destroy > > v3: Moved patch earlier in the series and removed

Re: [Intel-gfx] [PATCH i-g-t 2/4] scripts/trace.pl: Sort order

On 20/01/2018 00:24, john.c.harri...@intel.com wrote: From: John Harrison Add an extra level to the databse key sort so that the ordering is deterministic. If the time stamp matches, it now compares the key itself as well (context/seqno). This makes it much easier

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Allow clients to query own per-engine busyness

Quoting Tvrtko Ursulin (2018-01-22 11:45:04) > > On 22/01/2018 10:00, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-01-22 09:53:27) > >> > >> On 19/01/2018 21:08, Chris Wilson wrote: > >>> Quoting Tvrtko Ursulin (2018-01-19 13:45:24) > + case I915_CONTEXT_GET_ENGINE_BUSY: >

Re: [Intel-gfx] [PATCH v11 6/6] drm/i915: expose rcs topology through query uAPI

On 22/01/2018 08:21, Lionel Landwerlin wrote: With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate

Re: [Intel-gfx] [PATCH RFC 8/9] drm/i915: Allow default context priority to be set via cgroup parameter

Quoting Michel Dänzer (2018-01-22 09:50:38) > On 2018-01-20 11:40 AM, Chris Wilson wrote: > > > > Along this vein, it's worthwhile pointing out that the current scheduler > > is not even close to being the cgroup-enabled CFS implementation it > > needs to be to call itself a scheduler. (It's more

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Allow clients to query own per-engine busyness

Quoting Tvrtko Ursulin (2018-01-22 09:53:27) > > On 19/01/2018 21:08, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-01-19 13:45:24) > >> + case I915_CONTEXT_GET_ENGINE_BUSY: > >> + engine = intel_engine_lookup_user(i915, args->class, > >> +

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

Quoting Sagar Arun Kamble (2018-01-22 08:26:01) > +int intel_guc_log_relay_create(struct intel_guc *guc) > +{ > + struct drm_i915_private *dev_priv = guc_to_i915(guc); > + struct rchan *guc_log_relay_chan; > + size_t n_subbufs, subbuf_size; > + int ret; > + > + if

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

On 1/22/2018 3:41 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-01-22 08:26:02) Disabling GuC interrupts involves access to GuC IRQ control registers hence ensure device is RPM awake. v2: Add comment about need to synchronize flush work and log runtime destroy v3: Moved patch

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Increase render/media power gating hysteresis for gen9+ (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Increase render/media power gating hysteresis for gen9+ (rev2) URL : https://patchwork.freedesktop.org/series/36842/ State : success == Summary == Series 36842v2 series starting with [1/2] drm/i915: Increase render/media power

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

Quoting Sagar Arun Kamble (2018-01-22 10:38:10) > > > On 1/22/2018 3:46 PM, Chris Wilson wrote: > > Quoting Sagar Arun Kamble (2018-01-22 08:26:01) > >> +int intel_guc_log_relay_create(struct intel_guc *guc) > >> +{ > >> + struct drm_i915_private *dev_priv = guc_to_i915(guc); > >> +

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: expose RCS topology to userspace

== Series Details == Series: drm/i915: expose RCS topology to userspace URL : https://patchwork.freedesktop.org/series/36874/ State : warning == Summary == Test kms_flip: Subgroup flip-vs-expired-vblank-interruptible: fail -> PASS (shard-apl) fdo#102887

[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Intel-gfx] [PATCH 00/16] Adding NV12 support

This patch series is adding NV12 support for Gen >= 9 platforms. Current testing has been done on Gen9 and Gen10 only. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches

[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling v2: Review comments from Ville addressed NV12 case to be checked first for setting the

[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h |

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

From: Mahesh Kumar This will reduce number of arguments required to be passed in skl_compute_plane_wm function. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 7 insertions(+), 11

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements.

[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar NV12 formats have two registers for DDB. Verify both the registers for NV12 during verify_wm_state. v2: Addressed review comments by Maarten. Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1:

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

== Series Details == Series: series starting with [1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex URL : https://patchwork.freedesktop.org/series/36875/ State : failure == Summary == Test drv_suspend: Subgroup forcewake: skip

Re: [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Skip forcewake for ELSP submission

Quoting Tvrtko Ursulin (2018-01-22 09:50:57) > > On 20/01/2018 09:31, Chris Wilson wrote: > > Now that we can read the CSB from the HWSP, we may avoid having to > > perform mmio reads entirely and so forgo the rigmarole of the forcewake > > dance. > > > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Allow clients to query own per-engine busyness

On 19/01/2018 21:08, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-01-19 13:45:24) + case I915_CONTEXT_GET_ENGINE_BUSY: + engine = intel_engine_lookup_user(i915, args->class, + args->instance); + if (!engine)

Re: [Intel-gfx] [PATCH i-g-t 1/4] scripts/trace.pl: More hash key optimisations

On 20/01/2018 00:24, john.c.harri...@intel.com wrote: From: John Harrison Cache the key count value rather than querying the hash every time. This actually makes a difference? Just curious, I would have assumed Perl would know the size of it's arrays but maybe

Re: [Intel-gfx] [PATCH i-g-t 3/4] scripts/trace.pl: Calculate stats only after all munging

On 20/01/2018 00:24, john.c.harri...@intel.com wrote: From: John Harrison There are various statistics being calculated multiple times in multiple places while the log file is being read in. Some of these are then re-calculated when the database is munged to correct

Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Disable preemption and sleeping while using the punit sideband

Quoting Mika Kuoppala (2018-01-15 12:04:40) > Chris Wilson writes: > > > While we talk to the punit over its sideband, we need to prevent the cpu > > from sleeping in order to prevent a potential machine hang. > > > > Note that by itself, it appears that

Re: [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Skip forcewake for ELSP submission

On 20/01/2018 09:31, Chris Wilson wrote: Now that we can read the CSB from the HWSP, we may avoid having to perform mmio reads entirely and so forgo the rigmarole of the forcewake dance. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 12

Re: [Intel-gfx] [PATCH RFC 8/9] drm/i915: Allow default context priority to be set via cgroup parameter

On 2018-01-20 11:40 AM, Chris Wilson wrote: > > Along this vein, it's worthwhile pointing out that the current scheduler > is not even close to being the cgroup-enabled CFS implementation it > needs to be to call itself a scheduler. (It's more or less a no-op > scheduler.) It may be premature to

Re: [Intel-gfx] [PATCH] drm/i915: Protect WC stash allocation against direct reclaim

On 21 January 2018 at 17:31, Chris Wilson wrote: > As we attempt to allocate pages for use in a new WC stash, direct > reclaim may run underneath us and fill up the WC stash. We have to be > careful then not to overflow the pvec. > > Fixes: 66df1014efba ("drm/i915: Keep

[Intel-gfx] ✓ Fi.CI.BAT: success for Adding NV12 support (rev7)

== Series Details == Series: Adding NV12 support (rev7) URL : https://patchwork.freedesktop.org/series/28103/ State : success == Summary == Series 28103v7 Adding NV12 support https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/7/mbox/ fi-bdw-5557u total:288 pass:267

Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Enable interrupts before resuming GuC during runtime resume

Quoting Sagar Arun Kamble (2018-01-22 08:26:03) > GuC log streaming needs interrupts enabled prior to GuC resume but > runtime pm interrupt setup was happening post GuC resume. Fix it. > While at it, fix the unwinding of steps in the runtime suspend path. > > Bugzilla:

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Allow clients to query own per-engine busyness

On 22/01/2018 10:00, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-01-22 09:53:27) On 19/01/2018 21:08, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-01-19 13:45:24) + case I915_CONTEXT_GET_ENGINE_BUSY: + engine = intel_engine_lookup_user(i915, args->class, +

[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and

[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. Signed-off-by: Mahesh Kumar ---

[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not

[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

Re: [Intel-gfx] [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.

On Fri, Jan 19, 2018 at 04:05:24PM -0800, Rodrigo Vivi wrote: > SKUs that lacks on the full port F split will just time out > when touching this power well bits, causing a noisy warn. > > This macro style is a deviation from the original definition in use > for other platforms, but it at least

Re: [Intel-gfx] [RFC 4/6] drm/i915/pmu: Add queued counter

Quoting Tvrtko Ursulin (2018-01-22 18:43:56) > From: Tvrtko Ursulin > > We add a PMU counter to expose the number of requests which have been > submitted from userspace but are not yet runnable due dependencies and > unsignaled fences. > > This is useful to analyze the

Re: [Intel-gfx] [PATCH 2/3] drm/i915/: Initialise trans_min for skl_compute_transition_wm()

Quoting Rodrigo Vivi (2017-11-16 01:12:15) > On Wed, Nov 15, 2017 at 10:50:35AM +, Chris Wilson wrote: > > clang spots > > > > drivers/gpu/drm/i915/intel_pm.c:4655:6: warning: variable 'trans_min' is > > used uninitialized whenever 'if' condition is false > > [-Wsometimes-uninitialized] > >

Re: [Intel-gfx] [PATCH] drm/i915: Move LRC register offsets to a header file

Quoting Michel Thierry (2018-01-22 20:06:32) > Newer platforms may have subtle offset changes, which will increase the > number of defines, so it is probably better to start moving them to its > own header file. Also move the macros used while setting the reg state. I was scared that we might be

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move LRC register offsets to a header file

== Series Details == Series: drm/i915: Move LRC register offsets to a header file URL : https://patchwork.freedesktop.org/series/36930/ State : success == Summary == Series 36930v1 drm/i915: Move LRC register offsets to a header file

Re: [Intel-gfx] [PATCH] drm/i915: Move LRC register offsets to a header file

On 1/22/2018 12:14 PM, Chris Wilson wrote: Quoting Michel Thierry (2018-01-22 20:06:32) Newer platforms may have subtle offset changes, which will increase the number of defines, so it is probably better to start moving them to its own header file. Also move the macros used while setting the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Restore HDCP DRM_INFO when with no downstream

== Series Details == Series: drm/i915: Restore HDCP DRM_INFO when with no downstream URL : https://patchwork.freedesktop.org/series/36921/ State : success == Summary == Series 36921v1 drm/i915: Restore HDCP DRM_INFO when with no downstream

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD

On Mon, Jan 22, 2018 at 12:07:28PM +0530, Sharma, Shashank wrote: > Regards > > Shashank > > > On 1/13/2018 2:34 AM, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > The LG 4k TV I have doesn't deassert HPD when I turn the TV off, but > > when I turn it back

[Intel-gfx] ✓ Fi.CI.BAT: success for Queued/runnable/running engine stats

== Series Details == Series: Queued/runnable/running engine stats URL : https://patchwork.freedesktop.org/series/36926/ State : success == Summary == Series 36926v1 Queued/runnable/running engine stats https://patchwork.freedesktop.org/api/1.0/series/36926/revisions/1/mbox/ Test

[Intel-gfx] [RFC 4/6] drm/i915/pmu: Add queued counter

From: Tvrtko Ursulin We add a PMU counter to expose the number of requests which have been submitted from userspace but are not yet runnable due dependencies and unsignaled fences. This is useful to analyze the overall load of the system. v2: * Rebase for name change

[Intel-gfx] [RFC 5/6] drm/i915/pmu: Add runnable counter

From: Tvrtko Ursulin We add a PMU counter to expose the number of requests with resolved dependencies waiting for a slot on the GPU to run. This is useful to analyze the overall load of the system. v2: Don't limit to gen8+. v3: * Rebase for dynamic sysfs. * Drop

[Intel-gfx] [RFC 3/6] drm/i915: Keep a count of requests submitted from userspace

From: Tvrtko Ursulin Keep a count of requests submitted from userspace and not yet runnable due unresolved dependencies. v2: Rename and move under the container struct. (Chris Wilson) Signed-off-by: Tvrtko Ursulin ---

[Intel-gfx] [RFC 1/6] drm/i915/pmu: Fix enable count array size and bounds checking

From: Tvrtko Ursulin Enable count array is supposed to have one counter for each possible engine sampler. As such array sizing and bounds checking is not correct when more engine samplers are added. At the same time tidy the assert for readability and robustness.

[Intel-gfx] [RFC 6/6] drm/i915/pmu: Add running counter

From: Tvrtko Ursulin We add a PMU counter to expose the number of requests currently executing on the GPU. This is useful to analyze the overall load of the system. v2: * Rebase. * Drop floating point constant. (Chris Wilson) Signed-off-by: Tvrtko Ursulin

[Intel-gfx] [RFC 2/6] drm/i915: Keep a count of requests waiting for a slot on GPU

From: Tvrtko Ursulin Keep a per-engine number of runnable (waiting for GPU time) requests. v2: * Move queued increment from insert_request to execlist_submit_request to avoid bumping when re-ordering for priority. * Support the counter on the ringbuffer submission

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/breadcrumbs: Drop request reference for the signaler thread

== Series Details == Series: drm/i915/breadcrumbs: Drop request reference for the signaler thread URL : https://patchwork.freedesktop.org/series/36908/ State : success == Summary == Series 36908v1 drm/i915/breadcrumbs: Drop request reference for the signaler thread

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement display w/a #1143 (rev2)

== Series Details == Series: drm/i915: Implement display w/a #1143 (rev2) URL : https://patchwork.freedesktop.org/series/36813/ State : success == Summary == Series 36813v2 drm/i915: Implement display w/a #1143 https://patchwork.freedesktop.org/api/1.0/series/36813/revisions/2/mbox/ Test

Re: [Intel-gfx] [RFC v2 0/6] Queued/runnable/running engine stats

Quoting Tvrtko Ursulin (2018-01-22 18:43:52) > From: Tvrtko Ursulin > > Per-engine queue depths are an interesting metric for analyzing the system > load > and also for users who wish to use it to load balance their submissions based > on it. > > In this version I

[Intel-gfx] [PATCH] drm/i915: Move LRC register offsets to a header file

Newer platforms may have subtle offset changes, which will increase the number of defines, so it is probably better to start moving them to its own header file. Also move the macros used while setting the reg state. Signed-off-by: Michel Thierry Cc: Michal Wajdeczko

Re: [Intel-gfx] [RFC 2/6] drm/i915: Keep a count of requests waiting for a slot on GPU

Quoting Tvrtko Ursulin (2018-01-22 18:43:54) > From: Tvrtko Ursulin > > Keep a per-engine number of runnable (waiting for GPU time) requests. > > v2: > * Move queued increment from insert_request to execlist_submit_request to >avoid bumping when re-ordering for

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

On Tue, 2018-01-23 at 02:43 +, Pandiyan, Dhinakaran wrote: > > > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote: > > On some Cannonlake SKUs we have a dedicated Aux for port F, > > that is only the full split between port A and port E. > > > > There is still no Aux E for Port E, as

[Intel-gfx] ✗ Fi.CI.IGT: failure for Queued/runnable/running engine stats

== Series Details == Series: Queued/runnable/running engine stats URL : https://patchwork.freedesktop.org/series/36926/ State : failure == Summary == Test kms_flip: Subgroup busy-flip-interruptible: pass -> FAIL (shard-apl) fdo#103257 Subgroup

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5) URL : https://patchwork.freedesktop.org/series/36828/ State : failure == Summary == Test kms_flip: Subgroup flip-vs-panning-vs-hang-interruptible:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Move LRC register offsets to a header file (rev3)

== Series Details == Series: drm/i915: Move LRC register offsets to a header file (rev3) URL : https://patchwork.freedesktop.org/series/36930/ State : failure == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-tilingchange: fail -> PASS (shard-apl)

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/dp: Add HBR3 support in existing DRM DP helpers

== Series Details == Series: series starting with [1/2] drm/dp: Add HBR3 support in existing DRM DP helpers URL : https://patchwork.freedesktop.org/series/36931/ State : failure == Summary == Test kms_cursor_legacy: Subgroup short-flip-after-cursor-atomic-transitions:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915: Increase render/media power gating hysteresis for gen9+ (rev3)

== Series Details == Series: series starting with [v2] drm/i915: Increase render/media power gating hysteresis for gen9+ (rev3) URL : https://patchwork.freedesktop.org/series/36842/ State : success == Summary == Series 36842v3 series starting with [v2] drm/i915: Increase render/media power

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

On 1/22/2018 4:17 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-01-22 10:38:10) On 1/22/2018 3:46 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-01-22 08:26:01) +int intel_guc_log_relay_create(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv =

[Intel-gfx] [PATCH v2] drm/i915: Increase render/media power gating hysteresis for gen9+

On gen9+, after an idle period the HW will disable the entire power well to conserve power (by preventing current leakage). It takes around a 100 microseconds to bring the power well back online afterwards. With the current hysteresis value of 25us (really 25 * 1280ns), we do not have sufficient

[Intel-gfx] [PATCH] drm/i915: Replace open-coded wait-for loop

Now that we can pass arbitrary commands into the base __wait_for() macro, we can reimplement the open-coded wait-for inside i915_gem_idle_work_handler() using the macro. This means that instead of using ktime, we now use jiffies, and benefit from the exponential sleep backoff that allows a fast

Re: [Intel-gfx] [PATCH 02/10] drm/i915/cnl: Add AUX-F support

On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote: > On some Cannonlake SKUs we have a dedicated Aux for port F, > that is only the full split between port A and port E. > > There is still no Aux E for Port E, as in previous platforms, > because port_E still means shared lanes with port A.

[Intel-gfx] [PATCH] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.

SKUs that lacks on the full port F split will just time out when touching this power well bits, causing a noisy warn. v2: Suggested-by: Imre. Temporarily remove the aux pw id after setting it instead of duplicating and redefining everything. Cc: Lucas De Marchi Cc:

[Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

On some Cannonlake SKUs we have a dedicated Aux for port F, that is only the full split between port A and port E. There is still no Aux E for Port E, as in previous platforms, because port_E still means shared lanes with port A. v2: Rebase. v3: Add couple missed PORT_F cases on intel_dp. v4:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/breadcrumbs: Drop request reference for the signaler thread

== Series Details == Series: drm/i915/breadcrumbs: Drop request reference for the signaler thread URL : https://patchwork.freedesktop.org/series/36908/ State : failure == Summary == Test kms_cursor_crc: Subgroup cursor-256x256-suspend: incomplete -> PASS

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4) URL : https://patchwork.freedesktop.org/series/36828/ State : success == Summary == Series 36828v4 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5) URL : https://patchwork.freedesktop.org/series/36828/ State : success == Summary == Series 36828v5 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

On Mon, Jan 22, 2018 at 01:49:19PM -0800, Michel Thierry wrote: > > > > diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h > > > > b/drivers/gpu/drm/i915/intel_lrc_reg.h > > > > new file mode 100644 > > > > index ..f50d63cb4b66 > > > > --- /dev/null > > > > +++

[Intel-gfx] [PATCH v3] drm/i915: Move LRC register offsets to a header file

Newer platforms may have subtle offset changes, which will increase the number of defines, so it is probably better to start moving them to its own header file. Also move the macros used while setting the reg state. v2: Rename to intel_lrc_reg.h, to be consistent with i915_reg.h and

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

On 1/22/2018 4:31 PM, Lucas De Marchi wrote: So for this file what I understand is that it should be: // SPDX-License-Identifier: MIT // Copyright (C) 2014-2018 Intel Corporation So be it. ___ Intel-gfx mailing list

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move LRC register offsets to a header file (rev3)

== Series Details == Series: drm/i915: Move LRC register offsets to a header file (rev3) URL : https://patchwork.freedesktop.org/series/36930/ State : success == Summary == Series 36930v3 drm/i915: Move LRC register offsets to a header file

[Intel-gfx] [PATCH 2/2] drm/dp: Add definitions for TPS4 bits and macros to check the support

DP 1.4 spec adds a TPS4 training pattern sequence required for HBR3. This patch adds the corresponding bit definitions in MAX_DOWNSPREAD register and TRAINING_PATTERN_SET and inline functions to check if this bit is set and for selecting a proper TRAINING_PATTERN_MASK that changed to 0x7 on DP

[Intel-gfx] [PATCH 1/2] drm/dp: Add HBR3 support in existing DRM DP helpers

Existing helpers add support upto HBR2. This patch adds support for HBR3 rate (8.1 Gbps) introduced as part of DP 1.4 specification. Cc: Rodrigo Vivi Cc: Jani Nikula Cc: dri-de...@lists.freedesktop.org Signed-off-by: Manasi Navare

[Intel-gfx] [PATCH] drm/i915: For HPD connected port use hpd_pin instead of port.

Let's try to simplify this mapping to hpd_pin -> bit instead using port. So for CNL with port F where we have this port using hdp_pin and bits of other ports we don't need to duplicated the mapping. But for now this is only a re-org with no functional change expected. v2: Add missing lines and

  1   2   >