Quoting Tvrtko Ursulin (2018-11-30 15:15:28)
>
> On 30/11/2018 11:43, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
> >> From: Tvrtko Ursulin
> >>
> >> Two simple selftests which test that both GT and engine workarounds are
> >> not lost after either a full GPU reset, or
On Fri, 30 Nov 2018 14:51:24 +0800
Zhenyu Wang wrote:
> This trys to make 'kvmgt' module as self loadable instead of loading
> by i915/gvt device model. So hypervisor specific module could be
> stand-alone, e.g only after loading hypervisor specific module, GVT
> feature could be enabled via
Hi,
On Fri, Nov 30, 2018 at 04:34:54PM +0100, Hans Verkuil wrote:
> On 11/30/18 16:16, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote:
> >> On 11/30/18 15:29, Ville Syrjälä wrote:
> >>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> Hi
Hi,
I am looking for a way to export the color encoding and range selection
to user space. I came across those properties and am wondering, why
they are meant only for non RGB color encodings. Would it be okay, to
modify them and use with RGB formats as well?
Regards,
Chris
On 02/19/2018 09:28
On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote:
> On 11/30/18 15:29, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> >> Hi Ville,
> >>
> >> As Christoph cannot respond till middle next week I can try to respond
> >> in his absence, as I am
On 30/11/2018 11:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:32:00)
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one
On Thu, Nov 29, 2018 at 10:36:13AM -0500, Sean Paul wrote:
> On Wed, Nov 28, 2018 at 5:07 AM Daniel Vetter wrote:
> >
> > I've misplaced two functions by accident:
> > - drm_atomic_helper_duplicate_state is really part of the
> > resume/suspend/shutdown device-wide helpers.
> > -
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev3)
URL : https://patchwork.freedesktop.org/series/53094/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
56cf8aa074f9 drm/fbdev: Make skip_vt_switch the default
-:22: ERROR:GIT_COMMIT_ID: Please use git
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1125245b3d4b drm/i915: Record GT workarounds in a list
-:460:
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5235 -> Patchwork_10981
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev3)
URL : https://patchwork.freedesktop.org/series/53094/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5234 -> Patchwork_10980
Summary
---
On 30/11/2018 11:45, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:59)
-static void whitelist_reg(struct whitelist *w, i915_reg_t reg)
+static void
+whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
- if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS))
-
On 30/11/2018 11:49, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:32:01)
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
== Series Details ==
Series: drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
URL : https://patchwork.freedesktop.org/series/53284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10965_full
On Fri, Nov 30, 2018 at 07:31:01AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ddi: Check for unexpectedly disabled transcoders
> URL : https://patchwork.freedesktop.org/series/53256/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5224_full ->
On 30/11/2018 11:24, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10975
On 30/11/2018 11:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the
>-Original Message-
>From: Roper, Matthew D
>Sent: Friday, November 30, 2018 4:38 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
>; Syrjala, Ville ;
>Sharma,
>Shashank
>Subject: Re: [v3 1/3] drm/i915/icl: Add icl pipe degamma and gamma support
>
>On Thu,
On Fri, Nov 30, 2018 at 03:04:40PM +0200, Martin Peres wrote:
>
>
> On 29/11/2018 19:36, Rodrigo Vivi wrote:
> > On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote:
> >> Hi,
> >>
> >>> -Original Message-
> >>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org]
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
On 29/11/2018 14:47, Patchwork wrote:
== Series Details ==
Series: drm/i915/icl: Remove Wa_1604302699
URL : https://patchwork.freedesktop.org/series/53244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5222 -> Patchwork_10955
On 29/11/2018 17:48, Patchwork wrote:
== Series Details ==
Series: drm/i915: Remove whitelist application from ringbuffer backend (rev3)
URL : https://patchwork.freedesktop.org/series/53243/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5224 -> Patchwork_10960
On 11/30/18 16:16, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote:
>> On 11/30/18 15:29, Ville Syrjälä wrote:
>>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
Hi Ville,
As Christoph cannot respond till middle next week I can try
Pushed to drm-intel-next-queued, thanks for the review Rodrigo.
On Thu, 2018-11-29 at 23:52 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5)
> URL : https://patchwork.freedesktop.org/series/53132/
> State : success
>
> ==
On Thu, 2018-11-29 at 17:00 -0800, Souza, Jose wrote:
> On Thu, 2018-11-29 at 15:33 -0800, Dhinakaran Pandiyan wrote:
> > On Mon, 2018-11-26 at 16:37 -0800, José Roberto de Souza wrote:
> > > EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP() was being set with the
> > > number
> > > of
> > > frames that it
== Series Details ==
Series: HuC Update for BXT
URL : https://patchwork.freedesktop.org/series/53332/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5236 -> Patchwork_10982
Summary
---
**FAILURE**
Serious unknown
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53291/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227_full -> Patchwork_10970_full
On Mon, Nov 26, 2018 at 04:07:59PM -0800, José Roberto de Souza wrote:
> This helps separate what capabilities are display capabilities.
>
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Suggested-by: Jani Nikula
> Suggested-by: Lucas De Marchi
> Signed-off-by: José Roberto de Souza
> ---
>
On 30/11/2018 11:43, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is
== Series Details ==
Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4)
URL : https://patchwork.freedesktop.org/series/49669/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10967_full
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.
Initially we only do this after GPU initialization.
v2:
Chris
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
v2:
* Simplify with kmemdup. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
---
From: Tvrtko Ursulin
Instead of having a separate list of white-listed registers we can
trivially move this to the common workarounds framework.
This brings us one step closer to the goal of driving all workaround
classes using the same code.
v2:
* Use GEM_DEBUG_WARN_ON for the sanity check.
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration
From: Tvrtko Ursulin
First two patches in this series fix losing of workarounds after engine reset
(https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started
happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds
of workarounds").
But since it was
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is not affecting workarounds not
belonging to itself.)
v2:
* Rebase for series
Quoting Tvrtko Ursulin (2018-11-30 17:44:09)
> From: Tvrtko Ursulin
>
> Two simple selftests which test that both GT and engine workarounds are
> not lost after either a full GPU reset, or after the per-engine ones.
>
> (Including checks that one engine reset is not affecting workarounds not
>
On Fri, 2018-11-30 at 11:35 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 17:00 -0800, Souza, Jose wrote:
> > On Thu, 2018-11-29 at 15:33 -0800, Dhinakaran Pandiyan wrote:
> > > On Mon, 2018-11-26 at 16:37 -0800, José Roberto de Souza wrote:
> > > > EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP()
Quoting Tvrtko Ursulin (2018-11-30 17:44:12)
> From: Tvrtko Ursulin
>
> The new workaround list allocator grows the list in chunks so will end up
> with some unused space. Trim it when the initialization phase is done to
> free up a tiny bit of slab.
>
> v2:
> * Simplify with kmemdup. (Chris
On Thu, Nov 29, 2018 at 08:21:42PM +0530, Uma Shankar wrote:
> Enable ICL pipe csc hardware. CSC block is enabled
> in CSC_MODE register instead of PLANE_COLOR_CTL.
>
> v2: Addressed Maarten's review comments.
>
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
Quoting Tvrtko Ursulin (2018-11-30 17:44:10)
> u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index dfafc3f710d6..4eead104cd9c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++
Quoting Tvrtko Ursulin (2018-11-30 17:44:07)
> From: Tvrtko Ursulin
>
> We stopped re-applying the GT workarounds after engine reset since commit
> 59b449d5c82a ("drm/i915: Split out functions for different kinds of
> workarounds").
>
> Issue with this is that some of the GT workarounds live in
== Series Details ==
Series: series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's
host_init (rev2)
URL : https://patchwork.freedesktop.org/series/53295/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5227_full -> Patchwork_10973_full
Quoting Tvrtko Ursulin (2018-11-30 17:44:07)
> +static void xcs_engine_wa_init(struct intel_engine_cs *engine)
> +{
> + struct drm_i915_private *i915 = engine->i915;
> + struct i915_wa_list *wal = >wa_list;
> +
> + if (IS_KABYLAKE(i915)) {
> + /*
Quoting Chris Wilson (2018-11-30 21:08:08)
> Quoting Tvrtko Ursulin (2018-11-30 17:44:10)
> > u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index dfafc3f710d6..4eead104cd9c
On Wed, Nov 28, 2018 at 07:46:06PM +, Ho, Kenny wrote:
>
> On Wed, Nov 28, 2018 at 4:14 AM Joonas Lahtinen
> wrote:
> > So we can only choose the lowest common denominator, right?
> >
> > Any core count out of total core count should translate nicely into a
> > fraction, so what would be
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5)
URL : https://patchwork.freedesktop.org/series/53132/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227_full -> Patchwork_10968_full
From: Anusha Srivatsa
We have an update for HuC for BXT.
Load the latest version.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
Quoting Tvrtko Ursulin (2018-11-30 17:44:11)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 91a750e90dc4..8f985c35ec92 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -452,6
I'll check on it.
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, 29 November, 2018 3:47 PM
> To: Vivi, Rodrigo
> Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> Runyan, Arthur J ; Pandiyan, Dhinakaran
>
> Subject: Re: [PATCH 4/9] drm/i915/icl: Do not
From: Tomasz Lis
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version
From: Tomasz Lis
The MOCS tables are going to be very similar across platforms.
To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.
v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
to
Quoting Tvrtko Ursulin (2018-11-30 17:44:06)
> From: Tvrtko Ursulin
>
> To enable later verification of GT workaround state at various stages of
> driver lifetime, we record the list of applicable ones per platforms to a
> list, from which they are also applied.
>
> The added data structure is
Quoting Chris Wilson (2018-11-30 21:04:46)
> Quoting Tvrtko Ursulin (2018-11-30 17:44:09)
> > From: Tvrtko Ursulin
> >
> > Two simple selftests which test that both GT and engine workarounds are
> > not lost after either a full GPU reset, or after the per-engine ones.
> >
> > (Including checks
This helps separate what capabilities are display capabilities.
v3: Moving display struct right after flags (Lucas)
Cc: Jani Nikula
Suggested-by: Jani Nikula
Suggested-by: Lucas De Marchi
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h
Right now it is decided if GEN has display by checking the num_pipes,
so lets make it explicit and use a macro.
Cc: Jani Nikula
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h
On 11/30/2018 03:15 PM, Imre Deak wrote:
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville Syrjälä
On Fri, Nov 30, 2018 at 03:14:28PM -0800, Anusha wrote:
> From: Anusha Srivatsa
>
> Fix indentation error in the commit:
> commit 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
>
> Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
> Reported-by: Dan
Quoting Lucas De Marchi (2018-11-30 23:19:18)
> On Fri, Nov 30, 2018 at 09:59:53PM +, Chris Wilson wrote:
> > Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > > From: Tomasz Lis
> > >
> > > The MOCS tables are going to be very similar across platforms.
> > >
> > > To reduce the amount of
Fix the intel_link_compute_m_n in case of display stream
compression. This patch passes the compressed_bpp to
intel_link_compute_m_n if compression is enabled.
Fixes: a4a15c80 ("drm/i915/dp: Compute DSC pipe config in atomic check")
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by:
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
URL : https://patchwork.freedesktop.org/series/53341/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e5e5d91459ef drm/i915: Add HAS_DISPLAY() and use it
cf3a99ffde76 drm/i915: Move
== Series Details ==
Series: i915/dp/fec: Fix static check warning
URL : https://patchwork.freedesktop.org/series/53342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10986
Summary
---
**SUCCESS**
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Source is required to comply to sink SU granularity when
> DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
> so adding the registers offsets.
>
> v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
>
> Cc: Dhinakaran Pandiyan
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC
URL : https://patchwork.freedesktop.org/series/53340/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M]
From: Anusha Srivatsa
Fix indentation error in the commit:
commit 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
Reported-by: Dan Carpenter
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> i915 yet don't support PSR in Apple panels, so lets keep it disabled
> while we work on that.
>
> v2: Renamed DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED to
> DP_DPCD_QUIRK_NO_PSR (Ville)
>
> Fixes: 598c6cfe0690 (drm/i915/psr:
Quoting Chris Wilson (2018-11-30 23:35:25)
> I may have misunderstood your intent (if the commits remained the same
> as before, you could have just requeued the earlier series for testing)
> as I thought your intent here was to get CI results before applying
> these patches (be that yourself or
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
Right, there is no bit in PSR2_CTL
Reviewed-by: Dhinakaran Pandiyan
> while PSR2 is active, so don't configure sink DPCD with a
> misleading value.
>
> v2:
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
v2: remove debug code that Imre found
BSpec: 21257
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Clint Taylor
---
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10987
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
URL : https://patchwork.freedesktop.org/series/53341/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add HAS_DISPLAY() and use it
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
> and this bit is only set for PSR1 move it to that block to make it
> more easy to read.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> In August 2018 the BSPEC changed the ICL port programming sequence to
> closely resemble earlier gen programming sequence.
>
> BSpec: 21257
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Rodrigo
On Fri, Nov 30, 2018 at 09:59:53PM +, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > From: Tomasz Lis
> >
> > The MOCS tables are going to be very similar across platforms.
> >
> > To reduce the amount of copied code, this patch rips the common part and
> > puts it
On Fri, Nov 30, 2018 at 11:35:25PM +, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-11-30 23:19:18)
> > On Fri, Nov 30, 2018 at 09:59:53PM +, Chris Wilson wrote:
> > > Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > > > From: Tomasz Lis
> > > >
> > > > The MOCS tables are going
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
URL : https://patchwork.freedesktop.org/series/53341/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10985
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> eDP spec states 2 different bits to enable sink to trigger a
> interruption when there is a CRC mismatch.
> DP_PSR_CRC_VERIFICATION is for PSR only and
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
With PSR short pulse
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Selective updates have a default granularity requirements as stated
> by eDP spec
Needs reference to the location in the spec.
> , so check if HW can match those requirements before
> enable PSR2.
typo: enabling*
>
> Cc:
== Series Details ==
Series: drm/i915/dp: Fix link compute m_n calc for DSC
URL : https://patchwork.freedesktop.org/series/53347/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10988
Summary
---
== Series Details ==
Series: series starting with [1/6] drm/i915: Complete the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53308/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5230_full -> Patchwork_10976_full
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230_full -> Patchwork_10975_full
== Series Details ==
Series: drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2)
URL : https://patchwork.freedesktop.org/series/53311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230_full -> Patchwork_10979_full
The following changes since commit 1baa34868b2c0a004dc595b20678145e3fff83e7:
Merge branch 'nxp_mc' of https://github.com/NXP/linux-firmware (2018-10-26
08:13:19 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware BXT_HUC
for you to fetch changes
From: Anusha Srivatsa
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c516c815..c681537bcb92 100644
---
Quoting Tvrtko Ursulin (2018-11-30 17:44:08)
> From: Tvrtko Ursulin
>
> Since we now have all the GT workarounds in a table, by adding a simple
> shared helper function we can now verify that their values are still
> applied after some interesting events in the lifetime of the driver.
>
>
On Fri, 2018-11-30 at 13:18 -0800, Souza, Jose wrote:
> On Fri, 2018-11-30 at 11:35 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 17:00 -0800, Souza, Jose wrote:
> > > On Thu, 2018-11-29 at 15:33 -0800, Dhinakaran Pandiyan wrote:
> > > > On Mon, 2018-11-26 at 16:37 -0800, José
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10974
From: Tvrtko Ursulin
The test was missing some magic ingredients to actually trigger the
resets.
In case of the full reset we need the I915_RESET_HANDOFF flag set, and in
case of engine reset we need a busy request.
Thanks to Chris for helping with reset magic.
v2:
* Grab RPM ref over reset.
On Thu, Nov 29, 2018 at 05:52:28PM +, Strasser, Kevin wrote:
> Daniel Vetter wrote:
> > Do we have end-to-end userspace for this?
>
> I have patches for IGT and I'm planning on adding usage code to Weston. Apart
> from that there is a Windows use case that Tina mentioned previously. I take
>
Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git
Quoting Tvrtko Ursulin (2018-11-30 08:02:53)
> From: Tvrtko Ursulin
>
> Pull out spinner code to a standalone file to enable it to be shortly used
> by other and new test cases.
>
> Plain code movement - no functional changes.
>
> Signed-off-by: Tvrtko Ursulin
Shiver me conflicts.
Impose a restraint that we have all vma pinned for a request prior to
its allocation. This is to simplify request construction, and should
facilitate unravelling the lock interdependencies later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++--
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
We inspect the requests under the assumption that they will be marked as
completed when they are removed from the queue. Currently however, in the
process of wedging the requests will be removed from the queue before they
are completed, so rearrange the code to complete the fences before the
locks
== Series Details ==
Series: series starting with [1/2] drm/i915:
s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/
URL : https://patchwork.freedesktop.org/series/53275/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10961_full
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