The Jasper Lake PCH follows ICP/TGP's south display behavior and is
identical to MCC graphics-wise except that it does not use the unusual
(port C -> TC1) pin mapping that MCC does.
Also, it turns out the extra PCH ID that we had previously thought was a
form of MCC is actually a second ID for
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
The heartbeat interval can be adjusted per-engine
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of
We perform timeslicing immediately upon receipt of a request that may be
put into the second ELSP slot. The idea behind this was that since we
didn't install the timer if the second ELSP slot was empty, we would not
have any idea of how long ELSP[0] had been running and so giving the
newcomer a
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 14 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
On schedule-out (CS completion) of a banned context, scrub the context
image so that we do not replay the active payload. The intent is that we
skip banned payloads on request submission so that the timeline
advancement continues on in the background. However, if we are returning
to a preempted
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure.
Separate each object class into a separate lock type to avoid lockdep
cross-contamination between paths (i.e. userptr!).
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 3 ++-
There is no significance to our delay before clearing the semaphore the
engine is waiting on, so release it as soon as we acknowledge the CS
update following our preemption request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
1 file changed, 3 insertions(+),
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately
== Series Details ==
Series: series starting with [v3,1/3] drm/i915: Add microcontrollers
documentation section
URL : https://patchwork.freedesktop.org/series/67986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7090 -> Patchwork_14796
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use endless batches and will disable
the
The Jasper Lake PCH follows ICP/TGP's south display behavior and is
identical to MCC graphics-wise except that it does not use the unusual
(port C -> TC1) pin mapping that MCC does.
Also, it turns out the extra PCH ID that we had previously thought was a
form of MCC is actually a second ID for
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH
URL : https://patchwork.freedesktop.org/series/67992/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7091 -> Patchwork_14799
Summary
---
**FAILURE**
== Series Details ==
Series: series starting with [01/10] drm/i915/gem: Distinguish each object type
URL : https://patchwork.freedesktop.org/series/67993/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7091 -> Patchwork_14800
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev4)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5b2a67fc7d74 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev4)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7091 -> Patchwork_14802
Summary
Gen12 display can decompress surfaces compressed by render engine with Clear
Color, add
a new modifier as the driver needs to know the surface was compressed by render
engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix
Quoting Ville Syrjälä (2019-10-14 20:23:42)
> On Wed, Oct 09, 2019 at 09:12:23PM -, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats
> > on SNB-BDW sprites (rev2)
> > URL :
On Mon, 14 Oct 2019 14:24:31 -0700
Matt Roper wrote:
> The Jasper Lake PCH follows ICP/TGP's south display behavior and is
> identical to MCC graphics-wise except that it does not use the unusual
> (port C -> TC1) pin mapping that MCC does.
>
> Also, it turns out the extra PCH ID that we had
== Series Details ==
Series: series starting with [1/3] drm/i915/perf: Add helper macros for
comparing with whitelisted registers
URL : https://patchwork.freedesktop.org/series/67987/
State : failure
== Summary ==
Applying: drm/i915/perf: Add helper macros for comparing with whitelisted
== Series Details ==
Series: series starting with [01/10] drm/i915/gem: Distinguish each object type
URL : https://patchwork.freedesktop.org/series/67993/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/gem: Distinguish each object type
Okay!
== Series Details ==
Series: kernel-doc: rename the kernel-doc directive 'functions' to 'specific'
URL : https://patchwork.freedesktop.org/series/67984/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7089 -> Patchwork_14795
== Series Details ==
Series: series starting with [01/10] drm/i915/gem: Distinguish each object type
URL : https://patchwork.freedesktop.org/series/67993/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
560c3f3d40a2 drm/i915/gem: Distinguish each object type
7b18d5f62f34
From: Dhinakaran Pandiyan
intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file
From: Dhinakaran Pandiyan
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and
From: Dhinakaran Pandiyan
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
include/drm/drm_fourcc.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Dhinakaran Pandiyan
intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 69
From: Dhinakaran Pandiyan
Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so
Gen12 display can decompress surfaces compressed by render engine with Clear
Color, add
a new modifier as the driver needs to know the surface was compressed by render
engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
Cc:
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Nanley G Chery
Cc: Matt Roper
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse
From: Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Nanley G Chery
Cc: Jason Ekstrand
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 11 +++
From: Dhinakaran Pandiyan
Easier to read if all the alignment changes are in one place and contained
within a function.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++--
1 file changed, 16
== Series Details ==
Series: drm/i915: Introduce Jasper Lake PCH (rev2)
URL : https://patchwork.freedesktop.org/series/67992/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7091 -> Patchwork_14801
Summary
---
Support for Clear Color is contained in the last two patches
submitted by Radhakrishna Sripada. The first 8 patches are
currently undergoing review/revision changes. The first 8 patches
are cherry-picked from the series
https://patchwork.freedesktop.org/series/67078/
Expecting feedback for the
== Series Details ==
Series: Add mipi dsi command mode support.
URL : https://patchwork.freedesktop.org/series/67974/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7086_full -> Patchwork_14792_full
Summary
---
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/perf: introduce a versioning of
the i915-perf uapi
URL : https://patchwork.freedesktop.org/series/67990/
State : failure
== Summary ==
Applying: drm/i915/perf: introduce a versioning of the i915-perf uapi
Using index info to
On Mon, 14 Oct 2019 15:43:41 -0700
Matt Roper wrote:
> The Jasper Lake PCH follows ICP/TGP's south display behavior and is
> identical to MCC graphics-wise except that it does not use the unusual
> (port C -> TC1) pin mapping that MCC does.
>
> Also, it turns out the extra PCH ID that we had
> -Original Message-
> From: Jani Nikula on October 13, 2019 11:00 PM
> On Sun, 13 Oct 2019, Changbin Du wrote:
> > The 'functions' directive is not only for functions, but also works for
> > structs/unions. So the name is misleading. This patch renames it to
> > 'specific', so now we
== Series Details ==
Series: kernel-doc: rename the kernel-doc directive 'functions' to 'specific'
URL : https://patchwork.freedesktop.org/series/67984/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8314c1dd258c kernel-doc: rename the kernel-doc directive 'functions' to
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev5)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e84d0c20bec1 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area (rev2)
URL : https://patchwork.freedesktop.org/series/67930/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7087_full -> Patchwork_14794_full
On 2019/10/15 上午1:39, Stefan Hajnoczi wrote:
On Fri, Oct 11, 2019 at 04:15:56PM +0800, Jason Wang wrote:
+struct virtio_mdev_device {
+ struct virtio_device vdev;
+ struct mdev_device *mdev;
+ unsigned long version;
+
+ struct virtqueue **vqs;
+ /* The lock to
On 2019/10/15 上午1:49, Stefan Hajnoczi wrote:
On Fri, Oct 11, 2019 at 04:15:50PM +0800, Jason Wang wrote:
There are hardware that can do virtio datapath offloading while having
its own control path. This path tries to implement a mdev based
unified API to support using kernel virtio driver to
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev5)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7091 -> Patchwork_14803
Summary
== Series Details ==
Series: drm/i915/execlists: Assert tasklet is locked for process_csb() (rev4)
URL : https://patchwork.freedesktop.org/series/67957/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7087_full -> Patchwork_14793_full
On Mon, Oct 14, 2019 at 08:48:48PM +, tim.b...@sony.com wrote:
>
>
> > -Original Message-
> > From: Jani Nikula on October 13, 2019 11:00 PM
> > On Sun, 13 Oct 2019, Changbin Du wrote:
> > > The 'functions' directive is not only for functions, but also works for
> > >
On 2019/10/15 上午1:23, Stefan Hajnoczi wrote:
On Fri, Oct 11, 2019 at 04:15:55PM +0800, Jason Wang wrote:
+ * @set_vq_cb: Set the interrut calback function for
s/interrut/interrupt/
s/calback/callback/
Fixed.
Thanks
___
On 2019-10-11 at 11:19:18 -0700, Juston Li wrote:
> This includes other platforms that utilize the same gen graphics as
> CFL: AML, WHL and CML.
>
> Signed-off-by: Juston Li
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Quoting Tvrtko Ursulin (2019-10-14 10:34:31)
>
> On 13/10/2019 21:30, Chris Wilson wrote:
> > Since commit e2144503bf3b ("drm/i915: Prevent bonded requests from
> > overtaking each other on preemption") we have restricted requests to run
> > on their chosen engine across preemption events. We can
On 14/10/2019 10:37, Chris Wilson wrote:
We rely on only the tasklet being allowed to call into process_csb(), so
assert that is locked when we do. As the tasklet uses a simple bitlock,
there is no strong lockdep checking so we must make do with a plain
assertion that the tasklet is running and
On 14/10/2019 10:07, Chris Wilson wrote:
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the
Quoting Tvrtko Ursulin (2019-10-14 10:59:44)
>
> On 14/10/2019 10:07, Chris Wilson wrote:
> > +static int __live_lrc_state(struct i915_gem_context *fixme,
> > + struct intel_engine_cs *engine,
> > + struct i915_vma *scratch)
> > +{
> > + struct
Quoting Tvrtko Ursulin (2019-10-14 11:17:54)
>
> On 14/10/2019 10:07, Chris Wilson wrote:
> > +static ssize_t
> > +caps_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> > +{
> > + struct intel_engine_cs *engine = kobj_to_engine(kobj);
> > + const char * const *repr;
>
Configure the transcoder to operate in TE GATE command mode
and take TE events from GPIO.
Also disable the periodic command mode, that GOP would have
programmed.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 32 ++
1 file changed, 32
In TE Gate mode, on every flip we need to set the
frame update request bit. After this bit is set
transcoder hardware will automatically send the
frame data to the panel when it receives the TE event.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c| 27
On Fri, 2019-10-11 at 16:49 -0700, James Ausmus wrote:
> On Wed, Sep 25, 2019 at 03:17:37PM +0300, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> >
> > Currently we
We need to configure TE interrupt in two places.
Port interrupt and DSI interrupt mask registers.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/i915_irq.c | 49 -
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git
Adding all the register definitions needed
for mipi dsi command mode.
Signed-off-by: Madhav Chauhan
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/i915_reg.h | 76 +
1 file changed, 68 insertions(+), 8 deletions(-)
diff --git
From: Madhav Chauhan
This patch adds a helper function to find encoder
if DSI is operating in command mode. This function
will be used while enabling/disabling TE interrupts
for DSI.
Signed-off-by: Madhav Chauhan
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c |
In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/i915_irq.c | 61 +
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
This series has mainly patches to configure the dsi in
command mode, TE event handling and initiate a frame
request to the panel. Floating the RFC for review wrt
the above mentioned implementation.
For now we are configuring the MIPI DSI to operate in
TE gate mode and take TE events via GPIO.
Transcoder timing calculation differ for command mode.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 56 +-
1 file changed, 37 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
We rely on only the tasklet being allowed to call into process_csb(), so
assert that is locked when we do. As the tasklet uses a simple bitlock,
there is no strong lockdep checking so we must make do with a plain
assertion that the tasklet is running and assume that we are the
tasklet!
v2: Fixup
We rely on only the tasklet being allowed to call into process_csb(), so
assert that is locked when we do. As the tasklet uses a simple bitlock,
there is no strong lockdep checking so we must make do with a plain
assertion that the tasklet is running and assume that we are the
tasklet!
v2: Fixup
Quoting Tvrtko Ursulin (2019-10-14 10:34:31)
>
> On 13/10/2019 21:30, Chris Wilson wrote:
> > Since commit e2144503bf3b ("drm/i915: Prevent bonded requests from
> > overtaking each other on preemption") we have restricted requests to run
> > on their chosen engine across preemption events. We can
Quoting Ramalingam C (2019-10-14 10:28:18)
> On 2019-10-13 at 21:30:12 +0100, Chris Wilson wrote:
> > Since commit e2144503bf3b ("drm/i915: Prevent bonded requests from
> > overtaking each other on preemption") we have restricted requests to run
> > on their chosen engine across preemption events.
On 12/10/2019 09:02, Chris Wilson wrote:
Just a parameter rename,
drivers/gpu/drm/i915/display/intel_display.c:14425: warning: Function parameter
or member '_new_plane_state' not described in 'intel_prepare_plane_fb'
drivers/gpu/drm/i915/display/intel_display.c:14425: warning: Excess function
On 14/10/2019 10:07, Chris Wilson wrote:
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell,
On 14/10/2019 10:41, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-14 10:34:31)
On 13/10/2019 21:30, Chris Wilson wrote:
Since commit e2144503bf3b ("drm/i915: Prevent bonded requests from
overtaking each other on preemption") we have restricted requests to run
on their chosen engine
Quoting Tvrtko Ursulin (2019-10-14 10:50:25)
>
> On 14/10/2019 10:41, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-14 10:34:31)
> >>
> >> On 13/10/2019 21:30, Chris Wilson wrote:
> >>> Since commit e2144503bf3b ("drm/i915: Prevent bonded requests from
> >>> overtaking each other on
On 14/10/2019 10:07, Chris Wilson wrote:
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185
On 14/10/2019 10:07, Chris Wilson wrote:
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this
Quoting Chris Wilson (2019-10-14 10:28:53)
> Quoting Chris Wilson (2019-10-14 10:27:59)
> > Quoting Tvrtko Ursulin (2019-10-14 10:25:04)
> > >
> > > On 13/10/2019 20:31, Chris Wilson wrote:
> > > > We rely on only the tasklet being allowed to call into process_csb(), so
> > > > assert that is
On 13/10/2019 12:45, Chris Wilson wrote:
drivers/gpu/drm/i915/intel_memory_region.o: in function `igt_mock_contiguous':
drivers/gpu/drm/i915/selftests/intel_memory_region.c:166: undefined reference
to `__umoddi3'
v2: promote target to u64 for consistency across all builds
Reported-by: kbuild
On Fri, 11 Oct 2019, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The first come first served apporoach to handling the VBT
> child device AUX ch conflicts has backfired. We have machines
> in the wild where the VBT specifies both port A eDP and
> port E DP (in that order) with port E being
There is no significance to our delay before clearing the semaphore the
engine is waiting on, so release it as soon as we acknowledge the CS
update following our preemption request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
1 file changed, 3 insertions(+),
On schedule-out (CS completion) of a banned context, scrub the context
image so that we do not replay the active payload. The intent is that we
skip banned payloads on request submission so that the timeline
advancement continues on in the background. However, if we are returning
to a preempted
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
The heartbeat interval can be adjusted per-engine
We perform timeslicing immediately upon receipt of a request that may be
put into the second ELSP slot. The idea behind this was that since we
didn't install the timer if the second ELSP slot was empty, we would not
have any idea of how long ELSP[0] had been running and so giving the
newcomer a
Since commit e2144503bf3b ("drm/i915: Prevent bonded requests from
overtaking each other on preemption") we have restricted requests to run
on their chosen engine across preemption events. We can take this
restriction into account to know that we will want to resubmit those
requests onto the same
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 14 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use endless batches and will disable
the
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure.
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++---
1 file changed, 166
We rely on only the tasklet being allowed to call into process_csb(), so
assert that is locked when we do. As the tasklet uses a simple bitlock,
there is no strong lockdep checking so we must make do with a plain
assertion that the tasklet is running and assume that we are the
tasklet!
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by:
Just a parameter rename,
drivers/gpu/drm/i915/display/intel_display.c:14425: warning: Function parameter
or member '_new_plane_state' not described in 'intel_prepare_plane_fb'
drivers/gpu/drm/i915/display/intel_display.c:14425: warning: Excess function
parameter 'new_state' description in
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately
On Fri, 11 Oct 2019, Sean Paul wrote:
> On Thu, Oct 10, 2019 at 04:35:56PM +0300, Jani Nikula wrote:
>> On Thu, 10 Oct 2019, Hans de Goede wrote:
>> > Hi Jani,
>> >
>> > During plumbers I had some discussions with Daniel about supporting
>> > OLED screens. Userspace may need to know that a panel
Op 10-10-2019 om 16:47 schreef Ville Syrjälä:
> On Thu, Oct 10, 2019 at 04:21:00PM +0200, Maarten Lankhorst wrote:
>> Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
>>> On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
We want to split drm_crtc_state into the user visible
== Series Details ==
Series: drm/i915/selftests: Fixup naked 64b divide
URL : https://patchwork.freedesktop.org/series/67947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7075_full -> Patchwork_14780_full
Summary
---
Separate each object class into a separate lock type to avoid lockdep
cross-contamination between paths (i.e. userptr!).
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 3 ++-
On 13/10/2019 20:31, Chris Wilson wrote:
We rely on only the tasklet being allowed to call into process_csb(), so
assert that is locked when we do. As the tasklet uses a simple bitlock,
there is no strong lockdep checking so we must make do with a plain
assertion that the tasklet is running and
== Series Details ==
Series: drm/i915/perf: Avoid polluting the i915_oa_config with error pointers
URL : https://patchwork.freedesktop.org/series/67949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7075 -> Patchwork_14782
On Sun, 13 Oct 2019, Changbin Du wrote:
> The 'functions' directive is not only for functions, but also works for
> structs/unions. So the name is misleading. This patch renames it to
> 'specific', so now we have export/internal/specific directives to limit
> the functions/types to be included in
On 2019-10-13 at 21:30:12 +0100, Chris Wilson wrote:
> Since commit e2144503bf3b ("drm/i915: Prevent bonded requests from
> overtaking each other on preemption") we have restricted requests to run
> on their chosen engine across preemption events. We can take this
> restriction into account to
Quoting Tvrtko Ursulin (2019-10-14 10:25:04)
>
> On 13/10/2019 20:31, Chris Wilson wrote:
> > We rely on only the tasklet being allowed to call into process_csb(), so
> > assert that is locked when we do. As the tasklet uses a simple bitlock,
> > there is no strong lockdep checking so we must
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