== Series Details ==
Series: series starting with [1/3] drm/i915/perf: Whitelist OA report trigger
registers
URL : https://patchwork.freedesktop.org/series/79571/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8759 -> Patchwork_18199
== Series Details ==
Series: series starting with [1/3] drm/i915/perf: Whitelist OA report trigger
registers
URL : https://patchwork.freedesktop.org/series/79571/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
451a46ae0075 drm/i915/perf: Whitelist OA report trigger registers
On Thu, Jul 16, 2020 at 03:05:49PM -0700, Matt Roper wrote:
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were
== Series Details ==
Series: series starting with [1/3] drm/i915/perf: Whitelist OA report trigger
registers
URL : https://patchwork.freedesktop.org/series/79571/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be
On 10/07/2020 18:10, Chris Wilson wrote:
[ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370 [i915]
[ 1413.563221]
[ 1413.563236] race at unknown origin, with read to 0x5bb6c478 of 8
bytes by task 9654 on cpu 1:
[ 1413.563548] __await_execution+0x217/0x370 [i915]
[
On 16/07/2020 10:16, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-07-16 10:01:15)
On 14/07/2020 10:47, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e0280a672f1d..aa7be7f05f8c 100644
---
Quoting Tvrtko Ursulin (2020-07-16 11:11:55)
>
>
> On 16/07/2020 10:16, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-07-16 10:01:15)
> >>
> >> On 14/07/2020 10:47, Chris Wilson wrote:
> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>
Quoting Tvrtko Ursulin (2020-07-16 09:41:17)
> Right I missed dma_fence_is_signaled calls i915_request_completed.
>
> In this case the remaining question is do we care about wait ioctl
> potentially returning before the hypothetical sync fence for the same
> request is signaled? This seems like
On 16/07/2020 10:46, Chris Wilson wrote:
Rather than manually implement our own module reference counting for perf
pmu events, finally realise that there is a module parameter to struct
pmu for this very purpose.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: sta...@vger.kernel.org
---
Chris Wilson writes:
> Since we assert that the kernel_context is using the perma-pinned HWSP,
> make it so.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/mock_engine.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff
On 16/07/2020 01:43, Dave Airlie wrote:
On Wed, 15 Jul 2020 at 00:35, Matthew Auld wrote:
On 13/07/2020 06:09, Dave Airlie wrote:
On Fri, 10 Jul 2020 at 22:00, Matthew Auld wrote:
We need to add support for pwrite'ing an LMEM object.
why? DG1 is a discrete GPU, these interfaces we
Fbc is causing random underruns in CI execution on TGL platforms.
Disabling the same while the problem is being debugged and analyzed.
Cc: Stanislav Lisovskiy
Cc: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 +++
1 file changed, 7 insertions(+)
Quoting Tvrtko Ursulin (2020-07-16 10:17:11)
>
> On 10/07/2020 18:10, Chris Wilson wrote:
> > [ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370 [i915]
> > [ 1413.563221]
> > [ 1413.563236] race at unknown origin, with read to 0x5bb6c478 of 8
> > bytes by task 9654 on
== Series Details ==
Series: drm/i915: Provide the perf pmu.module
URL : https://patchwork.freedesktop.org/series/79547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8753 -> Patchwork_18187
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Reduce i915_request.lock contention for i915_request_wait
(rev2)
URL : https://patchwork.freedesktop.org/series/79514/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8753 -> Patchwork_18188
On 15/07/2020 15:47, Chris Wilson wrote:
Quoting Chris Wilson (2020-07-15 15:47:15)
Quoting Tvrtko Ursulin (2020-07-15 13:26:23)
On 15/07/2020 13:06, Tvrtko Ursulin wrote:
On 15/07/2020 11:50, Chris Wilson wrote:
Currently, we use i915_request_completed() directly in
i915_request_wait()
== Series Details ==
Series: drm/i915/display/fbc: Disable fbc by default on TGL
URL : https://patchwork.freedesktop.org/series/79541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8753 -> Patchwork_18186
Summary
---
On 16/07/2020 09:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-07-16 09:41:17)
Right I missed dma_fence_is_signaled calls i915_request_completed.
In this case the remaining question is do we care about wait ioctl
potentially returning before the hypothetical sync fence for the same
Quoting Tvrtko Ursulin (2020-07-16 10:01:15)
>
> On 14/07/2020 10:47, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index e0280a672f1d..aa7be7f05f8c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++
Rather than manually implement our own module reference counting for perf
pmu events, finally realise that there is a module parameter to struct
pmu for this very purpose.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/i915_pmu.c | 7 ++-
== Series Details ==
Series: drm/i915/display/fbc: Disable fbc by default on TGL
URL : https://patchwork.freedesktop.org/series/79541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8753_full -> Patchwork_18186_full
Summary
== Series Details ==
Series: drm/i915: Reduce i915_request.lock contention for i915_request_wait
(rev2)
URL : https://patchwork.freedesktop.org/series/79514/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked
On 14/07/2020 10:47, Chris Wilson wrote:
Since the breadcrumb enabling/cancelling itself is serialised by the
breadcrumbs.irq_lock, with a bit of care we can remove the outer
A few sentences explaining this care would be really helpful for review.
serialisation with i915_request.lock for
== Series Details ==
Series: drm/i915: Provide the perf pmu.module
URL : https://patchwork.freedesktop.org/series/79547/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
Currently, we use i915_request_completed() directly in
i915_request_wait() and follow up with a manual invocation of
dma_fence_signal(). This appears to cause a large number of contentions
on i915_request.lock as when the process is woken up after the fence is
signaled by an interrupt, we will
Quoting Tvrtko Ursulin (2020-07-16 12:11:18)
>
> On 16/07/2020 10:37, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-07-16 10:17:11)
> >>
> >> On 10/07/2020 18:10, Chris Wilson wrote:
> >>> [ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370
> >>> [i915]
> >>> [
drm-misc-next-2020-07-16:
drm-misc-next for v5.9:
UAPI Changes:
Cross-subsystem Changes:
- Add ckoenig as dma-buf maintainer.
- Revert invalid fix for dma-fence-chain, and fix selftest.
- Add fixmes to amifb about APUS support.
- Use array3_size in fbcon_prepare_logo, and struct_size() in
On Thu, Jul 16, 2020 at 02:25:40PM +0530, Uma Shankar wrote:
> Fbc is causing random underruns in CI execution on TGL platforms.
> Disabling the same while the problem is being debugged and analyzed.
>
> Cc: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Signed-off-by: Uma Shankar
Acked-by: Ville
== Series Details ==
Series: drm/i915: Reduce i915_request.lock contention for i915_request_wait
(rev2)
URL : https://patchwork.freedesktop.org/series/79514/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8753_full -> Patchwork_18188_full
On Thu, Jul 16, 2020 at 03:38:03PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 16, 2020 at 02:25:40PM +0530, Uma Shankar wrote:
> > Fbc is causing random underruns in CI execution on TGL platforms.
> > Disabling the same while the problem is being debugged and analyzed.
> >
> > Cc: Stanislav
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists
URL : https://patchwork.freedesktop.org/series/79551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18189
We are using the i915_request.lock to serialise adding an execution
callback with __i915_request_submit. However, if we use an atomic
llist_add to serialise multiple waiters and then check to see if the
request is already executing, we can remove the irq-spinlock.
v2: Avoid using the irq_work
[ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370 [i915]
[ 1413.563221]
[ 1413.563236] race at unknown origin, with read to 0x5bb6c478 of 8
bytes by task 9654 on cpu 1:
[ 1413.563548] __await_execution+0x217/0x370 [i915]
[ 1413.563891]
On 16/07/2020 10:37, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-07-16 10:17:11)
On 10/07/2020 18:10, Chris Wilson wrote:
[ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370 [i915]
[ 1413.563221]
[ 1413.563236] race at unknown origin, with read to 0x5bb6c478
On 16/07/2020 12:15, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-07-16 12:11:18)
On 16/07/2020 10:37, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-07-16 10:17:11)
On 10/07/2020 18:10, Chris Wilson wrote:
[ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists
URL : https://patchwork.freedesktop.org/series/79551/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
83628de655db drm/i915: Be wary of data races when
== Series Details ==
Series: drm/i915: Provide the perf pmu.module
URL : https://patchwork.freedesktop.org/series/79547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8753_full -> Patchwork_18187_full
Summary
---
[ 1413.563200] BUG: KCSAN: data-race in __await_execution+0x217/0x370 [i915]
[ 1413.563221]
[ 1413.563236] race at unknown origin, with read to 0x5bb6c478 of 8
bytes by task 9654 on cpu 1:
[ 1413.563548] __await_execution+0x217/0x370 [i915]
[ 1413.563891]
One more complication of preempt-to-busy with respect to the virtual
engine is that we may have retired the last request along the virtual
engine at the same time as preparing to submit the completed request to
a new engine. That submit will be shortcircuited, but not before we have
updated the
Since the breadcrumb enabling/cancelling itself is serialised by the
breadcrumbs.irq_lock, with a bit of care we can remove the outer
serialisation with i915_request.lock for concurrent
dma_fence_enable_signaling(). This has the important side-effect of
eliminating the nested i915_request.lock
On 16/07/2020 12:33, Chris Wilson wrote:
We are using the i915_request.lock to serialise adding an execution
callback with __i915_request_submit. However, if we use an atomic
llist_add to serialise multiple waiters and then check to see if the
request is already executing, we can remove the
Now that we have serialised the request retirement's decoupling of the
breadcrumb from the engine with the request signaling, we know that
there should never be a stale breadcrumb attached to an unbound virtual
engine. We can now remove the fixup code that had to migrate the
breadcrumbs along with
We are using the i915_request.lock to serialise adding an execution
callback with __i915_request_submit. However, if we use an atomic
llist_add to serialise multiple waiters and then check to see if the
request is already executing, we can remove the irq-spinlock.
v2: Avoid using the irq_work
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists
URL : https://patchwork.freedesktop.org/series/79551/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit
Chris Wilson writes:
> We include a tasklet flush before waiting on a request as a precaution
> against the HW being lax in event signaling. We now have a precautionary
> flush in the engine's heartbeat and so do not need to be quite so
> zealous on every request wait. If we focus on the
Fbc is causing random underruns in CI execution on TGL platforms.
Disabling the same while the problem is being debugged and analyzed.
v2: Moved the check below the module param check (Ville)
Cc: Stanislav Lisovskiy
Cc: Ville Syrjälä
Signed-off-by: Uma Shankar
---
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Be wary of data races when
reading the active execlists
URL : https://patchwork.freedesktop.org/series/79556/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18190
On 16/07/2020 12:33, Chris Wilson wrote:
Since the breadcrumb enabling/cancelling itself is serialised by the
breadcrumbs.irq_lock, with a bit of care we can remove the outer
serialisation with i915_request.lock for concurrent
dma_fence_enable_signaling(). This has the important side-effect of
From: Patchwork
Sent: Thursday, July 16, 2020 9:13 PM
To: Shankar, Uma
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Disable fbc by default
on TGL (rev2)
Patch Details
Series:
drm/i915/display/fbc: Disable fbc by default on TGL (rev2)
URL:
== Series Details ==
Series: drm/i915/display/fbc: Disable fbc by default on TGL (rev2)
URL : https://patchwork.freedesktop.org/series/79541/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18191
Summary
On 15/07/2020 16:43, Maarten Lankhorst wrote:
Op 15-07-2020 om 13:51 schreef Chris Wilson:
Our goal is to pull all memory reservations (next iteration
obj->ops->get_pages()) under a ww_mutex, and to align those reservations
with other drivers, i.e. control all such allocations with the
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Be wary of data races when
reading the active execlists
URL : https://patchwork.freedesktop.org/series/79556/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, July 16, 2020 6:19 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display/fbc: Disable fbc by default
> on
> TGL
>
> On Thu, Jul 16, 2020 at 03:38:03PM +0300, Ville
On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote:
From: Piotr Maciejewski
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not enough for query mode used to measure a
single draw call or dispatch. Gen9-Gen11 are using current i915 perf
Quoting Tvrtko Ursulin (2020-07-16 16:29:37)
>
> On 16/07/2020 12:33, Chris Wilson wrote:
> > Now that we have serialised the request retirement's decoupling of the
> > breadcrumb from the engine with the request signaling, we know that
> > there should never be a stale breadcrumb attached to an
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Be wary of data races when
reading the active execlists
URL : https://patchwork.freedesktop.org/series/79556/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a9025407e910 drm/i915: Be wary of data races when
On Thu, Jul 16, 2020 at 08:28:57PM +0530, Uma Shankar wrote:
> Fbc is causing random underruns in CI execution on TGL platforms.
> Disabling the same while the problem is being debugged and analyzed.
>
> v2: Moved the check below the module param check (Ville)
>
> Cc: Stanislav Lisovskiy
> Cc:
On 16/07/2020 12:33, Chris Wilson wrote:
Now that we have serialised the request retirement's decoupling of the
breadcrumb from the engine with the request signaling, we know that
there should never be a stale breadcrumb attached to an unbound virtual
engine. We can now remove the fixup code
On 16/07/2020 12:33, Chris Wilson wrote:
One more complication of preempt-to-busy with respect to the virtual
engine is that we may have retired the last request along the virtual
engine at the same time as preparing to submit the completed request to
a new engine. That submit will be
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists
URL : https://patchwork.freedesktop.org/series/79551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8754_full -> Patchwork_18189_full
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists (rev2)
URL : https://patchwork.freedesktop.org/series/79551/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists (rev2)
URL : https://patchwork.freedesktop.org/series/79551/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
848b1076da85 drm/i915: Be wary of data races
From: Ville Syrjälä
Most of the HSW PCI IDs are upper case hex numbers, but a
few are lower case. Make it consistent so these don't
stick out like a sore thumb.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 6 +++---
1 file changed, 3 insertions(+), 3
From: Ville Syrjälä
Bunch of the SKL SKUs currently documented as GT3/4 seem to actually
be GT3e/4e. Fix up the comments.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
From: Alexei Podtelezhnikov
Add three new devices 0x1913, 0x1915, and 0x1917 also known as
iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15.
Signed-off-by: Alexei Podtelezhnikov
[vsyrjala: Split separate changes into separate patchs,
Sort the IDs]
Signed-off-by: Ville Syrjälä
---
From: Alexei Podtelezhnikov
Reclassify 0x192A according to specifications. Of note, the
second to last digit seems to correspond to GT#.
Signed-off-by: Alexei Podtelezhnikov
[vsyrjala: Split separate changes into separate patches]
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h |
From: Alexei Podtelezhnikov
Reclassify 0x0426 as GT3 (GT2+) according to specifications and the second
least significant digit.
Signed-off-by: Alexei Podtelezhnikov
[vsyrjala: s/GT2/GT3/ in the comment]
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 2 +-
1 file changed, 1
From: Alexei Podtelezhnikov
Reclassify 0x1923, 0x1927 according to specifications. Of note,
the second to last digit seems to correspond to GT#.
Signed-off-by: Alexei Podtelezhnikov
[vsyrjala: Split separate changes into separate patches,
Sort the IDs]
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä
I started by splitting Alexei's SKL PCI ID fix into
logical chunks, and then ocd kicked in a bit...
Cc: Alexei Podtelezhnikov
Alexei Podtelezhnikov (4):
drm/i915: Update Haswell PCI IDs
drm/i915: Reclassify SKL 0x192a as GT3
drm/i915: Reclassify SKL 0x1923 and 0x1927
From: Ville Syrjälä
Sort the SKL PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/i915_pciids.h
From: Ville Syrjälä
Sort the EHL/JSL PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/drm/i915_pciids.h
From: Ville Syrjälä
Sort the CFL PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/drm/i915_pciids.h
From: Ville Syrjälä
Sort the ICL PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/drm/i915_pciids.h
From: Ville Syrjälä
Sort the HSW PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git
== Series Details ==
Series: drm/i915: PCI ID cleanup
URL : https://patchwork.freedesktop.org/series/79561/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists (rev2)
URL : https://patchwork.freedesktop.org/series/79551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18193
== Series Details ==
Series: drm/i915/display/fbc: Disable fbc by default on TGL (rev2)
URL : https://patchwork.freedesktop.org/series/79541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8754 -> Patchwork_18191
Summary
Re-reported.
From: Shankar, Uma
Sent: Thursday, July 16, 2020 6:51 PM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Disable fbc by
default on TGL (rev2)
From: Patchwork
mailto:patchw...@emeril.freedesktop.org>>
On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote:
On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote:
From: Piotr Maciejewski
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not enough for query mode used to measure a
single
== Series Details ==
Series: drm/i915: PCI ID cleanup
URL : https://patchwork.freedesktop.org/series/79561/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18192
Summary
---
**SUCCESS**
No
From: Ville Syrjälä
WAC6entrylatency is trying to fix excessive rc6 entry latency caused
by the extra delay from FBC_LLC_READ_CTRL, which is there for some
extra sync with uncore for frame buffer caching in LLC.
Reading through the hsd the recommendation was to set the FBC_LLC_FULLY_OPEN
bit to
From: Ville Syrjälä
It's silly to have if(SKL) checks in gen9_init_clock_gating() when
we can just move those bits into skl_init_clock_gating().
I'm not entirely convinced we even need this w/a, or if we do
then maybe we want it for kbl/cfl as well. IIRC it was only
listed in the wadb, but that
On Wed, Jul 15, 2020 at 03:42:17PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst
>
> Make vdsc work when no output is enabled. The big joiner needs VDSC
> on the slave, so enable it and set the appropriate bits.
> Also update timestamping constants, because slave crtc's are not
> updated
From: Ville Syrjälä
Sort the CNL PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/drm/i915_pciids.h
From: Ville Syrjälä
Sort the CML PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/drm/i915_pciids.h
From: Ville Syrjälä
Sort the KBL PCI IDs numerically. Some order seems better than
randomness.
Cc: Alexei Podtelezhnikov
Signed-off-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/i915_pciids.h
After staring at the breadcrumb enabling/cancellation and coming to the
conclusion that the cause of the mysterious stale breadcrumbs must the
act of submitting a completed requests, we can then redirect those
completed requests onto a dedicated signaled_list at the time of
construction and so
Quoting Tvrtko Ursulin (2020-07-16 16:37:25)
>
> On 16/07/2020 12:33, Chris Wilson wrote:
> > One more complication of preempt-to-busy with respect to the virtual
> > engine is that we may have retired the last request along the virtual
> > engine at the same time as preparing to submit the
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Be wary of data races when
reading the active execlists
URL : https://patchwork.freedesktop.org/series/79556/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8754_full -> Patchwork_18190_full
On 16/07/2020 21:06, Umesh Nerlige Ramappa wrote:
On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote:
On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote:
From: Piotr Maciejewski
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not
== Series Details ==
Series: drm/i915/display/fbc: Disable fbc by default on TGL (rev2)
URL : https://patchwork.freedesktop.org/series/79541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8754_full -> Patchwork_18191_full
On Thu, Jul 16, 2020 at 09:44:46PM +0300, Lionel Landwerlin wrote:
On 16/07/2020 21:06, Umesh Nerlige Ramappa wrote:
On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote:
On 14/07/2020 10:22, Umesh Nerlige Ramappa wrote:
From: Piotr Maciejewski
i915 used to support time based
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Add compiler paranoia
for checking HWSP values
URL : https://patchwork.freedesktop.org/series/79565/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
31bcd6fa4b2a drm/i915/selftests: Add compiler
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Add compiler paranoia
for checking HWSP values
URL : https://patchwork.freedesktop.org/series/79565/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Add compiler paranoia
for checking HWSP values
URL : https://patchwork.freedesktop.org/series/79565/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18195
From: Maarten Lankhorst
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
Also update timestamping constants, because slave crtc's are not
updated in drm_atomic_helper_update_legacy_modeset_state().
This should be enough
Quoting Chris Wilson (2020-07-16 21:32:01)
> Add a SRM read back of the aux invalidation register after poking
> hsdes: 1809175790, as failing to do so leads to writes going astray.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169
> Signed-off-by: Chris Wilson
> Cc: Mika
== Series Details ==
Series: series starting with [v6,01/11] HAX to make DSC work on the icelake
test system (rev2)
URL : https://patchwork.freedesktop.org/series/79534/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6756ad0df458 HAX to make DSC work on the icelake test system
== Series Details ==
Series: series starting with [v6,01/11] HAX to make DSC work on the icelake
test system (rev2)
URL : https://patchwork.freedesktop.org/series/79534/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't
== Series Details ==
Series: series starting with [1/2] drm/i915: Move WaDisableDopClockGating:skl
to skl_init_clock_gating()
URL : https://patchwork.freedesktop.org/series/79563/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8757 -> Patchwork_18194
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