going to be enabled needs to take in consideration
> the debug field.
>
> v2: Using the switch/case that intel_psr2_enabled() already had to
> handle this(DK)
Reviewed-by: Dhinakaran Pandiyan
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Robert
7;Source PSR ctl' inside of the brackets, PSR mode and Enabled was
> squashed into PSR mode, some renames and reorders and we have this
> cleaner version. This will also make easy to parse debugfs for IGT
> tests.
>
> v2: Printing sink PSR version with only 2 hex digits as it i
is not supported, did
not work well enough for PSR1 IGTs either. In any case, are these
interrupts present on ICL?
> v2: Warning and not letting user set PSR_DEBUG_IRQ when PSR2 is
> enabled(Dhinakaran)
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Rob
; Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 32 +
>
> 1 file changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
t the expected values are set for the current frame and
> the
> previous ones too.
The values correspond to the last 8 frames actually.
>
> v2: Improved macros(Dhinakaran)
Reviewed-by: Dhinakaran Pandiyan
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Jos
t;
> v3:
> - reading PSR2_SU_STATUS registers together(Dhinakaran)
> - printing SU blocks of frames with 0 updates(Dhinakaran)
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 23
rwell and checking for a timeout? Or at
least mark up a non-existent port after the first timeout so that we
don't keep probing it.
This patch is an improvement over checking the VBT for all ports, so
Reviewed-by: Dhinakaran Pandiyan
>
> v2:
> - Fix IS_ICL_WITH_PORT_F, so it
HBR3 panels.
>
Sounds like TP3 and TP4 are used only with PSR1, please document that
in the commit message.
> Cc: Manasi Navare
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
>
> Still trying to understand how PSR1 was working on ICL while sending
> TP
t; added to VBT, so lets use it when available otherwise it will
> fallback to PSR1 wakeup time.
>
> BSpec: 20131
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8
> driv
also fixes the bug linked bellow were DRRS was
> left enabled together with PSR when enabling PSR from debugfs.
>
> v2: Handling missing case: disabled to PSR1
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341
> Cc: Maarten Lankhorst
> Cc: Dhinakaran Pandiyan
ed by it ever, but better to protect just in case:
>
>
> Reviewed-by: Rodrigo Vivi
>
>
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 3 +--
>
On Thu, 2019-04-04 at 14:41 -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2019-04-04 at 14:20 -0700, Rodrigo Vivi wrote:
> > On Thu, Apr 04, 2019 at 12:40:34PM -0700, Souza, Jose wrote:
> > > On Wed, 2019-04-03 at 17:31 -0700, Rodrigo Vivi wrote:
> > > > On Wed, Ap
On Wed, 2019-04-03 at 16:35 -0700, José Roberto de Souza wrote:
> Even when driver is reloaded and hits this scenario the PSR mutex
> should be initialized, otherwise reading PSR debugfs status will
> execute mutex_lock() over a mutex that was not initialized.
>
> Cc: Dhinakaran
On Wed, 2019-04-03 at 16:35 -0700, José Roberto de Souza wrote:
> Just moving it to reduce the tabs and avoid break code lines.
> No behavior changes intended here.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_irq.c | 63 +++--
> 1 file c
On Thu, 2019-04-04 at 17:32 -0700, Souza, Jose wrote:
> On Thu, 2019-04-04 at 17:22 -0700, Dhinakaran Pandiyan wrote:
> > On Wed, 2019-04-03 at 16:35 -0700, José Roberto de Souza wrote:
> > > Even when driver is reloaded and hits this scenario the PSR mutex
> > > shoul
that.
>
> Also removing BDW_EDP_PSR_BASE from GVT because it is not used as
> the only PSR register that GVT have is this one(SRD/PSR_CTL).
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de S
On Tue, 2019-03-26 at 16:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> 6bpc is only legal for RGB and RAW pixel encodings. For the rest
> the minimum is 8bpc. Set our lower limit accordingly.
Patch doesn't apply anymore, got a conflict in intel_drv.h.
> Signed-off-by: Ville Syrjälä
On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote:
> On Tue, Apr 09, 2019 at 01:28:18PM -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-03-26 at 16:25 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > 6bpc is only legal for RGB a
ght after reading the iir bits. I had noticed this a
while back but never got to changing it.
2) we don't DRM_ERROR() for unexpected PSR interrupts like how other handlers
do. Not sure what's the point though, other than getting to know that the
hardware is broken.
Ville, any i
NS2(trans, reg) (INTEL_INFO(dev_priv)-
_TRANS() and _MMIO_TRANS() name the first argument "tran"
Can you please keep the same name "tran"?
Reviewed-by: Dhinakaran Pandiyan
> > trans_offsets[(trans)] - \
>
> +
because it is not used as it
> is the only PSR register that GVT have.
>
> v4:
> - Moved definition of _TRANS2_PSR() and _MMIO_TRANS2_PSR() to the
> beginning of i915_reg.h (Jani)
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Ville Syrjä
Patch 2 will make that easy.
Dhinakaran Pandiyan(2)
[PATCH 2/3] drm/i915: Move audio_connector to intel_encoder
[PATCH 3/3] drm/i915: Fix enc_to_dig_port for MST encoders
Libin Yang(1)
[PATCH 1/3] drm/i915: start adding dp mst audio
___
Intel-gfx
From: Libin Yang
(This patch is developed by Dave Airlie originally)
This patch adds support for DP MST audio in i915.
Enable audio codec when DP MST is enabled if has_audio flag is set.
Disable audio codec when DP MST is disabled if has_audio flag is set.
Another separated patches to support
audio_connector from struct intel_digital_port to struct intel_encoder.
This also simplifies access to the right audio_connector from codec
functions in intel_audio.c that receive intel_encoder.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_audio.c | 10 --
drivers/gpu/drm/i915
When a MST encoder is passed to enc_to_dig_port(), the container_of() macro
does not return the digital port. Handle this by returning the member
"primary" in "struct intel_dp_mst_encoder"
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_drv.h | 16
P MST). This patch makes the API changes with dummy changes in the
audio driver (Thanks Libin). Implementation to fully enable DP MST audio
will follow later.
Dhinakaran Pandiyan(1):
drm/i915/dp: DP audio API changes for MST
___
Intel-gfx mailing list
Inte
abled, unsigned char *buf, int max_bytes);
struct i915_audio_component_audio_ops
- void (*pin_eld_notify)(void *audio_ptr, int port);
+ void (*pin_eld_notify)(void *audio_ptr, int port, int dev_id);
This patch makes dummy changes in the audio drivers for build to succeed.
Signed-off-by: Dhi
Currently we do not print the training pattern used in any of the DP link
training stages. Including this piece of information in debug messages will
help debugging.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6
We do not currently output enough information to help debugging DP link
training issues. For e.g., training pattern and link status information.
This series aims to correct that by adding debug messages that can help
developers.
Dhinakaran Pandiyan (4):
drm/i915/dp: Add debug messages to print
Since a DRM function that reads link DP link status is available, let's
use that instead of the i915 clone.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 15 +++
drivers/gpu/drm/i915/intel_dp_link_training.c | 11 ---
drivers/gp
A full dump of link status can be handy in debugging link training
failures. Let's add that to the debug messages when link training fails.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp_link_training.c | 11 +++
drivers/gpu/drm/i915/intel_drv.h
avoid that with these debug
messages in drm.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_dp_helper.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 091053e..d763b57 100644
A full dump of link status can be handy in debugging link training
failures. Let's add that to the debug messages when link training fails.
v2: Removing unrelated clean up (Jani)
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp_link_training.c | 11 +++
1
: Downgraded log level from error to debug (Chris)
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 53d97f6..9a80628 100644
--- a
need more changes.
Addressed review comments from Jani and Chris.
Dhinakaran Pandiyan (2):
drm/i915/dp: Add debug messages to print DP link training pattern
drm/i915/dp: Dump DP link status when link training stages fail
drivers/gpu/drm/i915/intel_dp.c | 13
No functional change. Organizing the declarations for functions
implemented in intel_dp_link_training.c
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_drv.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers
also fixes the bug linked bellow were DRRS was
> left enabled together with PSR when enabling PSR from debugfs.
>
> v2: Handling missing case: disabled to PSR1
>
> v3: Not duplicating the whole atomic state(Maarten)
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.c
also fixes the bug linked bellow were DRRS was
> left enabled together with PSR when enabling PSR from debugfs.
>
> v2: Handling missing case: disabled to PSR1
>
> v3: Not duplicating the whole atomic state(Maarten)
>
> v4: Adding back the missing call to intel_psr_irq
viewed-by: Dhinakaran Pandiyan
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
>
e DDI CRCs as
well, which should reflect the partial frame that PSR2 sends.
To get a better understanding, I'd like to know what the source for
mismatching CRCs is?
> So here it disables PSR2 and keep it disabled while user is
> requesting pipe CRC.
>
> BSpec: 7536
>
> Cc:
On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> DP CRCs don't really work on g4x. If you want any CRCs on DP you must
> select the CRC source before the port is enabled, otherwise the CRC
> source select bits simply ignore any writes to them. And once the
> port
On Thu, 2019-02-14 at 17:32 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The "pipe" and "pf" crc sources are in fact the same thing.
> > Remove the "pf" one.
&
On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On skl the crc registers were extended to provide plane crcs
> for up to 7 planes. Add the new crc sources.
>
> The current code uses the ivb+ register definitions for skl+
> which does happen to work as the plane1
RC_SOURCE_PLANE2:
> *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
> break;
> - case INTEL_PIPE_CRC_SOURCE_PF:
> + case INTEL_PIPE_CRC_SOURCE_PIPE:
Ah, source == "pipe" would have returned a failure here
although ivb_crc_source_valid() cons
On Fri, 2019-02-15 at 14:47 +0200, Ville Syrjälä wrote:
> On Thu, Feb 14, 2019 at 06:26:29PM -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > DP CRCs don't really wo
On Mon, 2019-02-18 at 19:57 +0200, Ville Syrjälä wrote:
> On Fri, Feb 15, 2019 at 09:43:37PM +, Pandiyan, Dhinakaran wrote:
> > On Fri, 2019-02-15 at 23:34 +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 15, 2019 at 01:06:32PM -0800, Dhinakaran Pandiyan
> > > wrote:
&g
is enabled by default tests like
> kms_pipe_crc_basic@read-crc-pipe-b are failling even with the patch
> that disable PSR2 when getting CRC.
Thanks!
>
> >
> > > Cc: Maarten Lankhorst
> > > Cc: Dhinakaran Pandiyan
> > > Signed-off-by: José Roberto de
nd keep it disabled while user is
> requesting pipe CRC.
>
> BSpec: 7536
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
>
On Sat, 2019-02-23 at 02:48 +, Souza, Jose wrote:
> On Fri, 2019-02-22 at 18:13 -0800, Dhinakaran Pandiyan wrote:
> > On Wed, 2019-02-13 at 18:02 -0800, José Roberto de Souza wrote:
> > > As stated in CRC_CTL spec, after PSR entry state CRC will not be
> > > calcu
gt; > CRC
> > > so lets rename ips_force_disable to crc_enabled, drop all this
> > > checks
> > > for pipe A and HSW and BDW and make it generic and
> > > hsw_compute_ips_config() will take care of all the checks removed
> > > from here.
> > >
&g
rtc_crc_prepare() and crc_enabled
> > >
> > > v2: Changed commit description to describe that PSR2 inhibit CRC
> > > calculations.
> > >
> > > Cc: Dhinakaran Pandiyan
> > > Cc: Ville Syrjälä
> > > Signed-off-by: José Roberto de Souza
> &g
d as true is necessary to atomic checks
> functions compute new PSR state, that is why it was added to
> intel_crtc_crc_prepare().
>
> v3: Reusing intel_crtc_crc_prepare() and crc_enabled
>
> v2: Changed commit description to describe that PSR2 inhibit CRC
> calculations.
>
inhibits CRC calculations causing CRC timeout errors in IGT
> tests.
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 17 +++--
> 2 files
t, explanation here not so sure...
> but if this is really right and I am missing something feel
> free to use:
>
>
> Reviewed-by: Rodrigo Vivi
>
> otherwise please change the msg.
>
> Thanks,
> Rodrigo.
>
> >
> > Cc: Dhinakaran Pandiyan
On Mon, 2019-03-04 at 10:40 -0800, Souza, Jose wrote:
> On Mon, 2019-03-04 at 10:31 -0800, Dhinakaran Pandiyan wrote:
> > On Fri, 2019-03-01 at 17:34 -0800, José Roberto de Souza wrote:
> > > Increase the idle frames to activate PSR1 to avoid CRC timeouts,
> > > a
On Mon, 2019-03-04 at 15:50 -0800, Rodrigo Vivi wrote:
> On Mon, Mar 04, 2019 at 03:06:05PM -0800, Anusha wrote:
> > From: Anusha Srivatsa
> >
> > Comet Lake PCH is based off of Cannon Point(CNP).
> > Add PCI ID for Comet Lake PCH.
> >
> > Cc: Rodrigo Vivi
> > Cc: Lucas De Marchi
> > Signed-of
are shorter
> - they follow the exact name we have on spec
+1 for the above reason.
>
> >
> > Also taking the oportunity to improve those macros.
> >
> > Cc: Rodrigo Vivi
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> &
cessary so this FIXME is not valid anymore.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
>
> Reviewed-by: Rodrigo Vivi
Acked-by: Dhinakaran Pandiyan
>
> > ---
> > drivers/gpu/drm/i915/intel_ps
en
> updates.
>
> About EDP_PSR2_FRAMES_BEFORE_ACTIVATE() it is the number of frames
> (not idle frames) that PSR2 hardware will wait to activate PSR2, so
> lets keep using the sink sync latency.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de So
TION is for PSR only and
> > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > 1 file changed,
ot;Apple" with specific model name?
> > > disabled
> > > while we work on that.
> > >
> > > Fixes: 598c6cfe0690 (drm/i915/psr: Enable PSR1 on gen-9+ HW)
Bugzilla please. Also Cc the bug reporter?
> > > Cc: Rodrigo Vivi
> > > Cc: Dhin
On Thu, 2018-11-29 at 17:00 -0800, Souza, Jose wrote:
> On Thu, 2018-11-29 at 15:33 -0800, Dhinakaran Pandiyan wrote:
> > On Mon, 2018-11-26 at 16:37 -0800, José Roberto de Souza wrote:
> > > EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP() was being set with the
> > > number
&g
On Fri, 2018-11-30 at 13:18 -0800, Souza, Jose wrote:
> On Fri, 2018-11-30 at 11:35 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 17:00 -0800, Souza, Jose wrote:
> > > On Thu, 2018-11-29 at 15:33 -0800, Dhinakaran Pandiyan wrote:
> > > > On Mon, 2
598c6cfe0690 (drm/i915/psr: Enable PSR1 on gen-9+ HW)
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/drm_dp_helper.c | 2 ++
> drivers/gpu/drm/i915/intel_psr.c | 6 ++
> include/drm/drm_dp_he
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
Right, there is no bit in PSR2_CTL
Reviewed-by: Dhinakaran Pandiyan
> while PSR2 is active, so don't configure sink DPCD with a
> misleading
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
> and this bit is only set for PSR1 move it to that block to make it
> more easy to read.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodr
short pulse handling implemented, I think we are ready for
this.
Reviewed-by: Dhinakaran Pandiyan
>
> Cc: Dhinakaran Pandiyan
> Reviewed-by: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+)
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Source is required to comply to sink SU granularity when
> DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
> so adding the registers offsets.
>
> v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
>
> Cc
ng*
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > i915 yet don't support PSR in Apple panels, so lets keep it
> > disabled
> > while we work on that.
> >
> > v2: Renamed DP_DPC
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> According to eDP spec, sink can required specific selective update
> granularity that source must comply.
> Here caching the value if required and checking if source supports
> it.
>
> Cc: Rodrigo Vivi
> Cc
On Mon, 2018-12-03 at 12:14 -0800, Souza, Jose wrote:
> On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > > i915 yet don't support PSR in Apple panels, so lets keep it
> > > disa
SR2_IDLE_FRAME_MAX
>
> In the next patch the new macros will be used.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
&g
On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza wrote:
> There is no issues changing the PSR variables even if PSR will be not
> enabled but it avoid having misleading values like have psr2_enabled
> set but enabled unset.
>
> Cc: Maarten Lankhorst
> Cc: Dhinaka
bugs.freedesktop.org/show_bug.cgi?id=108341
> Cc: Maarten Lankhorst
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/
On Mon, 2018-12-03 at 17:54 -0800, Souza, Jose wrote:
> On Mon, 2018-12-03 at 17:33 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza wrote:
> > > Changing the i915_edp_psr_debug was enabling, disabling or
> > > switching
&g
efault granularity in case DPCD read
> fails(Dhinakaran)
> - Changed DPCD error message level(Dhinakaran)
>
> v4:
> - Setting granularity to defaul when granularity read is equal to
> 0(Dhinakaran)
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: J
On Tue, 2018-12-04 at 10:52 -0800, Souza, Jose wrote:
> On Mon, 2018-12-03 at 18:58 -0800, Dhinakaran Pandiyan wrote:
> > On Mon, 2018-12-03 at 17:54 -0800, Souza, Jose wrote:
> > > On Mon, 2018-12-03 at 17:33 -0800, Dhinakaran Pandiyan wrote:
> > > > On Thu, 2
https://bugs.freedesktop.org/show_bug.cgi?id=108341
> > > Cc: Maarten Lankhorst
> > > Cc: Dhinakaran Pandiyan
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/intel_psr.c | 5 -
> > > 1 file changed, 4 insertion
CD_QUIRK_NO_PSR
>
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Dhinakaran Pandiyan
> Fixes: 7c5c641a930e (drm/i915: Disable PSR in Apple panels)
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> include/drm/drm_dp_helper.h | 2 +-
> 1 file
max_w = 5120;
> + max_h = 4096;
Verified against bspec.
Reviewed-by: Dhinakaran Pandiyan
> + } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
> max_w = 4096;
> max_h = 4096;
> } else if (IS_G4X(dev_priv
DSI implements it's own pre_enable hook, encoder output type is never
DSI.
Cc: Manasi Navare
Cc: Paulo Zanoni
Cc: James Ausmus
Fixes: fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming
sequence for Combo PHY DDI")
Signed-off-by: Dhinakaran Pandiyan
---
drive
On Fri, 2018-12-07 at 16:07 +0200, Imre Deak wrote:
> Hi DK,
>
> On Thu, Dec 06, 2018 at 03:43:55PM -0800, Dhinakaran Pandiyan wrote:
> > DSI implements it's own pre_enable hook, encoder output type is
> > never
> > DSI.
> >
> > Cc: Manasi Navare
On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We aren't supposed to force a stop+start between every i2c msg
> when performing multi message transfers. This should eg. cause
> the DDC segment address to be reset back to 0 between writing
> the segment address a
On Fri, 2018-12-07 at 12:45 -0800, Dhinakaran Pandiyan wrote:
> On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We aren't supposed to force a stop+start between every i2c msg
> > when performing multi message transfers. T
g
> messages are all writes. Also check that the length of each
> message isn't too long.
Right, the syntax for i2c_remote_read allows only 8 bits for length.
Reviewed-by: Dhinakaran Pandiyan
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_mst_topology
{
> ret = -EREMOTEIO;
> goto out;
> }
> diff --git a/include/drm/drm_dp_helper.h
> b/include/drm/drm_dp_helper.h
> index 2a3843f248cf..2a0fd9d7066e 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/
essed,
Reviewed-by: Dhinakaran Pandiyan
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 65
> ++-
> include/drm/drm_dp_helper.h | 1 +
> 2 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --g
On Fri, 2018-12-07 at 16:57 -0800, Dhinakaran Pandiyan wrote:
> On Fri, 2018-09-28 at 21:04 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Decode the NAK reply fields to make it easier to parse the logs.
>
> A lot better than seeing the error code
On Mon, 2018-12-10 at 18:39 +0200, Ville Syrjälä wrote:
> On Fri, Dec 07, 2018 at 12:45:25PM -0800, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > We aren't supposed to
WRITE requests")
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_dp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2d6c491a0542..d98805b517f0 100644
--- a/drivers/gpu/drm/drm_d
On Mon, 2018-12-10 at 23:29 +0200, Ville Syrjälä wrote:
> On Mon, Dec 10, 2018 at 01:07:49PM -0800, Dhinakaran Pandiyan wrote:
> > The Write_Status_Update_Request I2C transaction requires the MOT
> > bit to
> > be set, Change the logical AND to OR to fix what looks like a
introduced here does make sense.
Reviewed-by: Dhinakaran Pandiyan
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_he
going to be enabled needs to take in consideration
> the debug field.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> dif
; of 'Source PSR ctl' inside of the brackets, PSR mode and Enabled was
> squashed into Status, some renames and reorders and we have this
> cleaner version. This will also make easy to parse debugfs for IGT
> tests.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Su
gging for PSR2. Fix
that to reject debugfs writes?
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/intel_psr.c| 1 +
> 2 files changed, 2 insertio
rrent frame and
> the
> previous ones too.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_r
On Tue, 2018-12-11 at 04:44 -0800, Souza, Jose wrote:
> On Mon, 2018-12-10 at 22:51 -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> > > The old debugfs fields was not following a naming partern and it
> > >
gfs latter it will keep PSR and DRRS enabled causing possible
> > problems as DRRS will lower the refresh rate while PSR enabled.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341
> > Cc: Maarten Lankhorst
> > Cc: Dhinakaran Pandiyan
> > Sig
On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> The value of this registers will be used to test if PSR2 is doing
> selective update and if the number of blocks match with the expected.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Jos
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