Regards
Shashank
On 1/8/2019 11:10 AM, Shankar, Uma wrote:
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Sharma, Shashank
Sent: Thursday, December 20, 2018 11:47 PM
To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
dri-de
On 1/8/2019 12:10 PM, Shankar, Uma wrote:
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Sharma, Shashank
Sent: Thursday, December 20, 2018 11:54 PM
To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
dri-de...@lists.freedesktop.org
Hello Ville,
On 1/29/2019 9:33 PM, Ville Syrjälä wrote:
On Tue, Jan 29, 2019 at 03:57:29PM +, Shankar, Uma wrote:
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Ville Syrjälä
Sent: Tuesday, January 29, 2019 9:14 PM
To: Shankar, U
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, May 2, 2019 3:45 PM
> To: Sharma, Shashank
> Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville
> ; Lankhorst,
> Maarten
> Subject: Re: [Intel-gfx] [PATCH
Regards
Shashank
On 5/3/2019 9:20 PM, Ville Syrjälä wrote:
On Tue, Apr 30, 2019 at 08:51:08PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve wi
On 5/3/2019 8:35 PM, Ville Syrjälä wrote:
On Tue, Apr 30, 2019 at 08:51:06PM +0530, Shashank Sharma wrote:
From: Uma Shankar
Add macros to define multi segmented gamma registers
V2: Addressed Ville's comments:
Add gen-lable before bit definition
Addressed Jani's comment
On 5/6/2019 5:55 PM, Ville Syrjälä wrote:
On Mon, May 06, 2019 at 04:09:33PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 5/3/2019 9:20 PM, Ville Syrjälä wrote:
On Tue, Apr 30, 2019 at 08:51:08PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display
Regards
Shashank
On 5/6/2019 6:41 PM, Ville Syrjälä wrote:
On Mon, May 06, 2019 at 06:25:19PM +0530, Sharma, Shashank wrote:
On 5/6/2019 5:55 PM, Ville Syrjälä wrote:
On Mon, May 06, 2019 at 04:09:33PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 5/3/2019 9:20 PM, Ville Syrjälä
On 5/7/2019 7:57 PM, Ville Syrjälä wrote:
On Tue, May 07, 2019 at 07:26:44PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precis
sequence gives a proper white output.
Regards
Shashank
On 5/8/2019 6:35 PM, Sharma, Shashank wrote:
On 5/7/2019 7:57 PM, Ville Syrjälä wrote:
On Tue, May 07, 2019 at 07:26:44PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma
Hello Uma,
V7 looks good to me, please feel free to use for the whole series:
Reviewed-by: Shashank Sharma
Regards
Shashank
On 4/3/2019 1:50 AM, Uma Shankar wrote:
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after ble
per, Matthew D ;
> seanp...@chromium.org; brian.star...@arm.com; dcasta...@chromium.org;
> Sharma, Shashank
> Subject: Re: [v3 6/7] drm: Add Client Cap for advance gamma mode
>
> fre 2019-04-12 klockan 15:51 +0530 skrev Uma Shankar:
> > Introduced a client cap for advance cap mode
>
On 4/15/2019 7:42 PM, Lankhorst, Maarten wrote:
mån 2019-04-15 klockan 19:26 +0530 skrev Sharma, Shashank:
-Original Message-
From: Lankhorst, Maarten
Sent: Monday, April 15, 2019 4:28 PM
To: Shankar, Uma ; intel-gfx@lists.freedeskt
op.org; dri-
de...@lists.freedesktop.org
Cc: Syrjala
On 4/13/2019 12:00 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The pipe has a special HDR mode with higher precision when only
HDR planes are active. Let's use it.
Curiously this fixes the kms_color gamma/degamma tests when
using a HDR plane, which is always the case unless one hacks
the tes
On 4/26/2019 11:46 PM, Ville Syrjälä wrote:
On Fri, Apr 26, 2019 at 11:31:50PM +0530, Shashank Sharma wrote:
From: Uma Shankar
Add macros to define multi segmented gamma registers
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17
On 4/26/2019 11:59 PM, Ville Syrjälä wrote:
On Fri, Apr 26, 2019 at 11:31:51PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine pre
On 4/29/2019 5:19 PM, Ville Syrjälä wrote:
On Mon, Apr 29, 2019 at 05:00:21PM +0530, Sharma, Shashank wrote:
On 4/26/2019 11:59 PM, Ville Syrjälä wrote:
On Fri, Apr 26, 2019 at 11:31:51PM +0530, Shashank Sharma wrote:
ICL introduces a new gamma correction mode in display engine, called
multi
On 4/26/2019 8:07 PM, Ville Syrjälä wrote:
On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
On 4/13/2019 12:00 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The pipe has a special HDR mode with higher precision when only
HDR planes are active. Let's use it.
Curiously
On 4/29/2019 7:42 PM, Jani Nikula wrote:
On Fri, 26 Apr 2019, Shashank Sharma wrote:
From: Uma Shankar
Add macros to define multi segmented gamma registers
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1
On 4/30/2019 4:09 PM, Ville Syrjälä wrote:
On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote:
On 4/26/2019 8:07 PM, Ville Syrjälä wrote:
On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
On 4/13/2019 12:00 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The
Thanks for the review Rodrigo. My comments inline.
Regards
Shashank
On 7/1/2016 3:46 AM, Rodrigo Vivi wrote:
On Tue, Jun 21, 2016 at 8:00 AM, Shashank Sharma
wrote:
This patch adds lspcon support in dp_dual_mode helper.
lspcon is essentially a dp->hdmi dongle with dual personality.
LS mode:
Regards
Shashank
On 7/1/2016 4:00 AM, Rodrigo Vivi wrote:
On Tue, Jun 21, 2016 at 8:00 AM, Shashank Sharma
wrote:
This patch adds a new file, to accommodate lspcon support
for I915 driver. These functions probe, detect, initialize
and configure an on-board lspcon device during the driver
init
Regards
Shashank
On 7/1/2016 4:18 AM, Rodrigo Vivi wrote:
On Tue, Jun 21, 2016 at 8:00 AM, Shashank Sharma
wrote:
Many GEN9 boards come with on-board lspcon cards.
Fot these boards, VBT configuration should properly point out
if a particular port contains lspcon device, so that driver can
init
Regards
Shashank
On 7/1/2016 4:23 AM, Rodrigo Vivi wrote:
On Tue, Jun 21, 2016 at 8:00 AM, Shashank Sharma
wrote:
This patch adds initialization code for lspcon.
What we are doing here is:
- Check if lspcon is configured in VBT for this port
- If lspcon is configured, initial
Thanks. I forgot to mention, this code works without AVI IF too.
Regards
Shashank
-Original Message-
From: Vivi, Rodrigo
Sent: Wednesday, July 6, 2016 11:04 PM
To: Sharma, Shashank ;
intel-gfx@lists.freedesktop.org; rodrigo.v...@gmail.com
Cc: ville.syrj...@linux.intel.com; Zanoni
.com]
Sent: Wednesday, July 20, 2016 6:39 PM
To: Sharma, Shashank
Cc: intel-gfx@lists.freedesktop.org; rodrigo.v...@gmail.com; Vivi, Rodrigo
; Zanoni, Paulo R
Subject: Re: [PATCH v3 0/4] Enable lspcon support for GEN9 devices
On Tue, Jul 05, 2016 at 06:35:46PM +0530, Shashank Sharma wrote:
>
re welcome.
Regards
Shashank
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Wednesday, July 20, 2016 10:21 PM
To: Sharma, Shashank
Cc: intel-gfx@lists.freedesktop.org; rodrigo.v...@gmail.com; Vivi, Rodrigo
; Zanoni, Paulo R
Subject: Re: [PATCH v3 0/4] Enable l
] On Behalf Of Daniel Vetter
Sent: Wednesday, August 3, 2016 5:18 PM
To: Sharma, Shashank
Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
ville.syrj...@linux.intel.com; rodrigo.v...@gmail.com; Vetter, Daniel
Subject: Re: [PATCH 0/4]: Picture aspect ratio support in DRM layer
in our HWComposer, and I guess it would be
required for X and Wayland too, coz finally these guys issue the modeset.
So May be X server is not handling these flags, ignoring these flags, and
sending the flagless modeset back to libdrm.
Regards
Shashank
-Original Message-
From: Jose A
Thanks for the review, Sean.
My comments, inline.
Regards
Shashank
On 8/3/2016 11:10 PM, Sean Paul wrote:
On Wed, Aug 3, 2016 at 6:56 AM, Shashank Sharma
wrote:
This patch adds drm flag bits for aspect ratio information
Currently drm flag bits don't have field for mode's picture
aspect ratio
Regards
Shashank
On 8/3/2016 11:14 PM, Sean Paul wrote:
On Wed, Aug 3, 2016 at 6:56 AM, Shashank Sharma
wrote:
Current DRM layer functions dont parse aspect ratio information
s/dont/don't/
Got it.
while converting a user mode->kernel mode or viceversa. This
s/viceversa/vice versa/
Got
Hello Emil,
Thanks for your time.
I have got mixed opinion on this.
IMHO we should expose them to userspace too, as UI agents like Hardware
composer/X/Wayland must know what does these
flags means, so that they can display them on the end user screen (like
settings menu)
But few people ev
Thanks Daniel.
My comments, inline.
Regards
Shashank
On 8/4/2016 4:06 PM, Daniel Vetter wrote:
On Thu, Aug 04, 2016 at 03:46:09PM +0530, Sharma, Shashank wrote:
Hello Emil,
Thanks for your time.
I have got mixed opinion on this.
IMHO we should expose them to userspace too, as UI agents
Regards
Shashank
On 8/4/2016 5:04 PM, Emil Velikov wrote:
On 4 August 2016 at 11:16, Sharma, Shashank wrote:
Hello Emil,
Thanks for your time.
I have got mixed opinion on this.
IMHO we should expose them to userspace too, as UI agents like Hardware
composer/X/Wayland must know what does
Regards
Shashank
On 8/4/2016 7:46 PM, Jose Abreu wrote:
Hi Sharma,
On 03-08-2016 16:47, Sharma, Shashank wrote:
Hello Joes,
I've also seen this before and I am using them in order to pass HDMI
compliance. Without
these patches the compliance fails. Still, I've made some chang
Regards
Shashank
On 8/4/2016 9:39 PM, Daniel Vetter wrote:
On Thu, Aug 04, 2016 at 03:31:45PM +0100, Emil Velikov wrote:
On 4 August 2016 at 14:15, Sharma, Shashank wrote:
On 8/4/2016 5:04 PM, Emil Velikov wrote:
On 4 August 2016 at 11:16, Sharma, Shashank
wrote:
Hello Emil,
Thanks for
Regards
Shashank
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Shankar, Uma
> Sent: Friday, February 8, 2019 5:45 PM
> To: Ville Syrjälä
> Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville
> ; dri-
> de...@lists.freedesktop.org;
Regards
Shashank
On 2/8/2019 6:22 PM, Ville Syrjälä wrote:
On Fri, Feb 08, 2019 at 12:36:25PM +, Sharma, Shashank wrote:
Regards
Shashank
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Shankar, Uma
Sent: Friday, February 8, 2019
Regards
Shashank
On 2/8/2019 7:00 PM, Ville Syrjälä wrote:
On Fri, Feb 08, 2019 at 06:36:39PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 2/8/2019 6:22 PM, Ville Syrjälä wrote:
On Fri, Feb 08, 2019 at 12:36:25PM +, Sharma, Shashank wrote:
Regards
Shashank
-Original
Regards
Shashank
On 11/27/2018 10:10 PM, Uma Shankar wrote:
This patch adds a HDMI colorspace property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the col
Regards
Shashank
On 11/27/2018 10:10 PM, Uma Shankar wrote:
This patch adds a DP colorspace property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the
Regards
Shashank
On 9/21/2018 12:21 AM, Ville Syrjala wrote:
From: Ville Syrjälä
We'll be wanting to send more than just infoframes over HDMI. So add an
enum for other packet types.
TODO: Maybe just include the infoframe types in the packet type enum
and get rid of the infoframe type
Regards
Shashank
On 12/11/2018 11:44 PM, Uma Shankar wrote:
This patch adds a colorspace connector property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
th
Regards
Shashank
On 12/11/2018 11:44 PM, Uma Shankar wrote:
This patch attaches the colorspace connector property to the
hdmi connector. Based on colorspace change, modeset will be
triggered to switch to new colorspace.
Based on colorspace property value create an infoframe
with appropriate c
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
Signed-off-by: U
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Add bit field and macro for extended tag in CEA block. Also,
declare macros for HDR metadata block.
This should have been a part of patch, where these macros are being
used, so that we can see it being used properly. While re-basing c
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 45 ++
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_c
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Attach HDR metadata property to connector object.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
HDR source metadata set and get property implemented in this
patch.
Again, HDR output metadata ? How about re-arranging the line like "This
patch implements get() and set() functions for HDR output metadata
property" just to make it
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The s
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions
supported.
Would it be possible to add some details about HLG ?
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 4
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i9
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
From: Ville Syrjälä
Function argument for hdmi_drm_infoframe_log is made constant.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Jani
> Nikula
> Sent: Friday, August 30, 2019 7:06 PM
> To: Manna, Animesh ; intel-gfx@lists.freedesktop.org
> Cc: Thierry, Michel
> Subject: Re: [Intel-gfx] [PATCH v4 02/10] drm/i915/
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Jani
> Nikula
> Sent: Friday, August 30, 2019 7:02 PM
> To: Manna, Animesh ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v4 08/10] drm/i915/dsb: Enable gamma lut
>
On 9/3/2019 1:29 PM, Jani Nikula wrote:
On Tue, 03 Sep 2019, "Sharma, Shashank" wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Jani
Nikula
Sent: Friday, August 30, 2019 7:02 PM
To: Manna, Animesh ;
Hello Ville,
On 9/3/2019 10:50 PM, Ville Syrjälä wrote:
On Tue, Sep 03, 2019 at 10:22:25PM +0530, Shashank Sharma wrote:
Blurry outputs during upscaling the buffer, is a generic problem of gfx
industry. One of the major reason behind this blurriness is the
interpolation of pixel values used by
On 9/4/2019 12:58 PM, Jani Nikula wrote:
On Tue, 03 Sep 2019, Shashank Sharma wrote:
If the upscaling ratio is a complete integer, Intel display HW can
pickup special scaling mode, which can produce better non-blurry
outputs. This patch adds a check to indicate if this is such an upscaling
opp
On 9/4/2019 1:08 PM, Ramalingam C wrote:
On 2019-09-03 at 22:22:26 +0530, Shashank Sharma wrote:
If the upscaling ratio is a complete integer, Intel display HW can
pickup special scaling mode, which can produce better non-blurry
outputs. This patch adds a check to indicate if this is such an up
On 9/4/2019 5:56 PM, Ville Syrjälä wrote:
On Wed, Sep 04, 2019 at 08:32:09AM +0530, Sharma, Shashank wrote:
Hello Ville,
On 9/3/2019 10:50 PM, Ville Syrjälä wrote:
On Tue, Sep 03, 2019 at 10:22:25PM +0530, Shashank Sharma wrote:
Blurry outputs during upscaling the buffer, is a generic
On 9/7/2019 4:37 PM, Animesh Manna wrote:
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro r
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALI
On 9/7/2019 4:37 PM, Animesh Manna wrote:
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v
On 9/7/2019 4:37 PM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneou
On 9/7/2019 4:37 PM, Animesh Manna wrote:
The lifetime of command buffer can be controlled by the dsb user
throuh refcount. Added refcount mechanism is dsb get/put call
which create/destroy dsb context.
Cc: Jani Nikula
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i9
> -Original Message-
> From: Manna, Animesh
> Sent: Monday, September 9, 2019 10:27 PM
> To: Sharma, Shashank ; intel-
> g...@lists.freedesktop.org
> Cc: Thierry, Michel ; Nikula, Jani
> ;
> Vivi, Rodrigo
> Subject: Re: [PATCH v5 05/11] drm/i915/d
info.h
@@ -135,6 +135,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
Looks good to me,
Feel free to use: Reviewed-by: Shashank Sharma
- Sh
rs/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,6 +67,7 @@
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
+#include "display/intel_dsb.h"
#include "display/intel_fron
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is
d intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val);
#endif
Looks good to me,
Please feel free to use Reviewed-by: Shashank Sharma
- Shashank
On 9/12/2019 6:37 PM, Animesh Manna wrote:
On 9/12/2019 6:30 PM, Sharma, Shashank wrote:
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank"
wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. G
ipe) * 0x1000 + (id) * 100)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
Looks good to me,
Please feel free to use Reviewed-by: Shash
ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
With or without suggested change above: Feel free to use
Reviewed-by: Shashank Sharma
- Shashank
#endif /* _I915_REG_H_ */
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On 9/12/2019 12:41 AM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultane
On 9/12/2019 7:09 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commi
] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- .has_global_mocs = 1
+ .has_global_mocs = 1, \
+ .display.has_dsb = 1
Looks good to me, feel free to use:
Reviewed-by: Shashank Sharma
- Shashank
static const
On 9/18/2019 1:27 PM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneo
On 9/18/2019 1:27 PM, Animesh Manna wrote:
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
Do
On 9/19/2019 10:08 PM, Jani Nikula wrote:
On Wed, 18 Sep 2019, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initi
Hello Uma,
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com
size_t size);
ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame,
void *buffer, size_t size);
int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame);
+int hdmi_drm_infoframe_init(struct hdmi_drm
On 3/11/2019 9:27 AM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comme
On 3/11/2019 9:28 AM, Uma Shankar wrote:
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve an
On 3/20/2019 12:47 PM, Shankar, Uma wrote:
-Original Message-
From: Sharma, Shashank
Sent: Friday, March 15, 2019 1:01 PM
To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
de...@lists.freedesktop.org
Cc: Lankhorst, Maarten ; Syrjala, Ville
; emil.l.veli...@gmail.com; brian.star
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
Signed-off-by: Uma Shankar
---
drive
On 3/20/2019 4:18 PM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comme
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
1 file changed, 13 insertions
_infoframe *frame);
enum hdmi_spd_sdi {
HDMI_SPD_SDI_UNKNOWN,
With that minor comment related to description fixed, this patch looks
good to me. Please feel free to use:
Reviewed-by: Shashank Sharma
- Shashank
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On 3/20/2019 4:18 PM, Uma Shankar wrote:
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++
On 3/20/2019 4:18 PM, Uma Shankar wrote:
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 fil
Hello Ram,
On 7/2/2019 11:24 AM, Ramalingam C wrote:
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check is mov
Regards
Shashank
On 7/9/2019 7:39 AM, Ramalingam C wrote:
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check i
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