On Tue, Feb 13, 2018 at 09:57:47AM +0000, Tvrtko Ursulin wrote:
> From: Chris Wilson <ch...@chris-wilson.co.uk>
> 
> As we peek inside struct device to query members guarded by CONFIG_PM,
> so must be the code.
> 
> Reported-by: kbuild test robot <fengguang...@intel.com>
> Fixes: 1fe699e30113 ("drm/i915/pmu: Fix sleep under atomic in RC6 readout")
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20180207160428.17015-1-ch...@chris-wilson.co.uk
> (cherry picked from commit 05273c950a3c93c5f96be8807eaf24f2cc9f1c1e)

All 4 patches applied to fixes.
Thanks for backporting and for adding cherry-picked message.

> ---
>  drivers/gpu/drm/i915/i915_pmu.c | 33 +++++++++++++++++++++++----------
>  1 file changed, 23 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index e13859aaa2a3..0e9b98c32b62 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -409,22 +409,32 @@ static int i915_pmu_event_init(struct perf_event *event)
>       return 0;
>  }
>  
> -static u64 get_rc6(struct drm_i915_private *i915, bool locked)
> +static u64 __get_rc6(struct drm_i915_private *i915)
>  {
> -     unsigned long flags;
>       u64 val;
>  
> -     if (intel_runtime_pm_get_if_in_use(i915)) {
> -             val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
> -                                                VLV_GT_RENDER_RC6 :
> -                                                GEN6_GT_GFX_RC6);
> +     val = intel_rc6_residency_ns(i915,
> +                                  IS_VALLEYVIEW(i915) ?
> +                                  VLV_GT_RENDER_RC6 :
> +                                  GEN6_GT_GFX_RC6);
>  
> -             if (HAS_RC6p(i915))
> -                     val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> +     if (HAS_RC6p(i915))
> +             val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> +
> +     if (HAS_RC6pp(i915))
> +             val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
> +
> +     return val;
> +}
>  
> -             if (HAS_RC6pp(i915))
> -                     val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
> +static u64 get_rc6(struct drm_i915_private *i915, bool locked)
> +{
> +#if IS_ENABLED(CONFIG_PM)
> +     unsigned long flags;
> +     u64 val;
>  
> +     if (intel_runtime_pm_get_if_in_use(i915)) {
> +             val = __get_rc6(i915);
>               intel_runtime_pm_put(i915);
>  
>               /*
> @@ -481,6 +491,9 @@ static u64 get_rc6(struct drm_i915_private *i915, bool 
> locked)
>       }
>  
>       return val;
> +#else
> +     return __get_rc6(i915);
> +#endif
>  }
>  
>  static u64 __i915_pmu_event_read(struct perf_event *event, bool locked)
> -- 
> 2.14.1
> 
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