This patch is the rest part of the introducing PAT interface patch series.
Please review. :) Thanks.
-----Original Message-----
From: Wang, Zhi A
Sent: Thursday, September 21, 2017 8:29 PM
To: intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org
Cc: joonas.lahti...@linux.intel.com; ch...@chris-wilson.co.uk;
zhen...@linux.intel.com; Wang, Zhi A <zhi.a.w...@intel.com>; Widawsky, Benjamin
<benjamin.widaw...@intel.com>; Vivi, Rodrigo <rodrigo.v...@intel.com>
Subject: [PATCH v18 1/2] drm/i915: Do not allocate unused PPAT entries
Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry allocation during
initialization.
v17:
- Refine ppat_index() and move the comments. (Joonas)
v8:
- Move ppat_index() into i915_gem_gtt.c. (Chris)
- Change the name of ppat_bits_to_index to ppat_index.
Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Signed-off-by: Zhi Wang <zhi.a.w...@intel.com>
Cc: Ben Widawsky <benjamin.widaw...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 52 ++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 731ce22..43e0d23 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -230,9 +230,11 @@ static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
switch (level) {
case I915_CACHE_NONE:
+ /* Uncached objects, mostly for scanout */
pte |= PPAT_UNCACHED;
break;
case I915_CACHE_WT:
+ /* for scanout with eLLC */
pte |= PPAT_DISPLAY_ELLC;
break;
default:
@@ -249,6 +251,7 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
pde |= addr;
if (level != I915_CACHE_NONE)
+ /* for normal objects, no eLLC */
pde |= PPAT_CACHED_PDE;
else
pde |= PPAT_UNCACHED;
@@ -2988,6 +2991,14 @@ static unsigned int chv_private_pat_match(u8 src, u8 dst)
INTEL_PPAT_PERFECT_MATCH : 0;
}
+/* PPAT index = 4 * PAT + 2 * PCD + PWT */ static inline unsigned int
+ppat_index(unsigned int bits) {
+ return (4 * !!(bits & _PAGE_PAT) +
+ 2 * !!(bits & _PAGE_PCD) +
+ !!(bits & _PAGE_PWT));
+}
+
static void cnl_setup_private_ppat(struct intel_ppat *ppat) {
ppat->max_entries = 8;
@@ -2997,18 +3008,14 @@ static void cnl_setup_private_ppat(struct intel_ppat
*ppat)
/* XXX: spec is unclear if this is still needed for CNL+ */
if (!USES_PPGTT(ppat->i915)) {
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE),
GEN8_PPAT_UC);
return;
}
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
- __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
- __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
- __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
- __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(0));
- __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(1));
- __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(2));
- __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(3));
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_WB |
GEN8_PPAT_LLC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), GEN8_PPAT_WT |
GEN8_PPAT_LLCELLC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), GEN8_PPAT_WB |
+GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
}
/* The GGTT and PPGTT need a private PPAT setup in order to handle
cacheability @@ -3035,18 +3042,14 @@ static void bdw_setup_private_ppat(struct
intel_ppat *ppat)
* So we can still hold onto all our assumptions wrt cpu
* clflushing on LLC machines.
*/
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE),
GEN8_PPAT_UC);
return;
}
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); /* for
normal objects, no eLLC */
- __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); /* for
something pointing to ptes? */
- __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); /* for
scanout with eLLC */
- __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); /*
Uncached objects, mostly for scanout */
- __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(0));
- __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(1));
- __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(2));
- __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(3));
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_WB |
GEN8_PPAT_LLC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), GEN8_PPAT_WT |
GEN8_PPAT_LLCELLC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), GEN8_PPAT_WB |
+GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
}
static void chv_setup_private_ppat(struct intel_ppat *ppat) @@ -3075,14
+3078,11 @@ static void chv_setup_private_ppat(struct intel_ppat *ppat)
* in order to keep the global status page working.
*/
- __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 1, 0);
- __alloc_ppat_entry(ppat, 2, 0);
- __alloc_ppat_entry(ppat, 3, 0);
- __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
+ /* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), CHV_PPAT_SNOOP);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), 0);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), 0);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), CHV_PPAT_SNOOP);
}
static void gen6_gmch_remove(struct i915_address_space *vm)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
