Hi Jean,
> From: Jean-Philippe Brucker
> Sent: Monday, July 16, 2018 6:52 PM
> On 16/07/18 07:49, Lu Baolu wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for first
> > level, second level, nested and
Hi Alex
On Mon, Jul 16, 2018 at 03:17:57PM -0600, Alex Williamson wrote:
> > static bool vfio_pci_nointx(struct pci_dev *pdev)
> > {
> > + /*
> > +* Per PCI, no VF's should have INTx
> > +* Simply disable it here
> > +*/
> > + if (pdev->is_virtfn)
> > + return true;
>
On Mon, 16 Jul 2018 13:42:25 -0700
Ashok Raj wrote:
> PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions.
>
> Some SRIOV devices have some bugs in RTL and VF's end up reading 1
> instead of 0 for the PIN.
>
> We could enforce it by default in vfio_pci_nointx.
>
> Reported-by:
PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions.
Some SRIOV devices have some bugs in RTL and VF's end up reading 1
instead of 0 for the PIN.
We could enforce it by default in vfio_pci_nointx.
Reported-by: Gage Eads
Tested-by: Gage Eads
Signed-off-by: Ashok Raj
Cc:
Hi Robin,
On 07/13/2018 01:09 PM, Robin Murphy wrote:
On 13/07/18 17:27, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add the SMMU node and IOMMU parameters to the
Stratix10 Device Tree.
Signed-off-by: Thor Thayer
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 44
On 21/06/18 08:27, Yong Wu wrote:
> Hi Matthias,
>
> A gentle ping on this.
>
> On Thu, 2018-05-24 at 20:35 +0800, Yong Wu wrote:
>> This patch adds decriptions for mt2712 IOMMU and SMI.
>>
>> In order to balance the bandwidth, mt2712 has two M4Us, two
>> smi-commons, 10 smi-larbs. and
On 7/16/2018 2:25 PM, Rafael J. Wysocki wrote:
On Thu, Jul 12, 2018 at 2:41 PM, Vivek Gautam
wrote:
Hi Rafael,
On Wed, Jul 11, 2018 at 4:06 PM, Vivek Gautam
wrote:
Hi Rafael,
On 7/11/2018 3:23 PM, Rafael J. Wysocki wrote:
On Sunday, July 8, 2018 7:34:12 PM CEST Vivek Gautam wrote:
Hi,
On 16/07/18 07:49, Lu Baolu wrote:
> Intel vt-d rev3.0 [1] introduces a new translation mode called
> 'scalable mode', which enables PASID-granular translations for
> first level, second level, nested and pass-through modes. The
> vt-d scalable mode is the key ingredient to enable Scalable
Hi,
On Mon, Jul 16, 2018 at 12:11 PM, Vivek Gautam
wrote:
> HI Rafael,
>
>
>
> On 7/16/2018 2:21 PM, Rafael J. Wysocki wrote:
>>
>> On Thu, Jul 12, 2018 at 12:57 PM, Vivek Gautam
>> wrote:
[cut]
Although, given the PM
subsystem internals, the suspend function wouldn't be called on
HI Rafael,
On 7/16/2018 2:21 PM, Rafael J. Wysocki wrote:
On Thu, Jul 12, 2018 at 12:57 PM, Vivek Gautam
wrote:
Hi,
On Wed, Jul 11, 2018 at 6:21 PM, Tomasz Figa wrote:
On Wed, Jul 11, 2018 at 8:11 PM Rafael J. Wysocki wrote:
On Wed, Jul 11, 2018 at 12:55 PM, Vivek Gautam
wrote:
Hi
On Thu, Jul 12, 2018 at 2:41 PM, Vivek Gautam
wrote:
> Hi Rafael,
>
>
> On Wed, Jul 11, 2018 at 4:06 PM, Vivek Gautam
> wrote:
>> Hi Rafael,
>>
>>
>>
>> On 7/11/2018 3:23 PM, Rafael J. Wysocki wrote:
>>>
>>> On Sunday, July 8, 2018 7:34:12 PM CEST Vivek Gautam wrote:
From: Sricharan R
On Thu, Jul 12, 2018 at 12:57 PM, Vivek Gautam
wrote:
> Hi,
>
>
> On Wed, Jul 11, 2018 at 6:21 PM, Tomasz Figa wrote:
>> On Wed, Jul 11, 2018 at 8:11 PM Rafael J. Wysocki wrote:
>>>
>>> On Wed, Jul 11, 2018 at 12:55 PM, Vivek Gautam
>>> wrote:
>>> > Hi Rafael,
>>> >
>>> >
>>> > On Wed, Jul 11,
On 2018.07.16 14:02:12 +0800, Lu Baolu wrote:
> Hi Joerg,
>
> The graphic guys are looking forward to having this in 4.18.
> Is it possible to take it in the following rcs?
>
This breakes intel gfx driver in 4.18 when gfx dmar is on.
Please include this fix ASAP.
Tested-by: Zhenyu Wang
On 07/09/2018 02:19 PM, Marek Szyprowski wrote:
> cma_alloc() function doesn't really support gfp flags other than
> __GFP_NOWARN, so convert gfp_mask parameter to boolean no_warn parameter.
>
> This will help to avoid giving false feeling that this function supports
> standard gfp flags and
On 07/09/2018 02:19 PM, Marek Szyprowski wrote:
> The CMA memory allocator doesn't support standard gfp flags for memory
> allocation, so there is no point having it as a parameter for
> dma_alloc_from_contiguous() function. Replace it by a boolean no_warn
> argument, which covers all the
Deferred invalidation is an ECS specific feature. It will not be
supported when IOMMU works in scalable mode. As we deprecated the
ECS support, remove deferred invalidation and cleanup the code.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by:
This patch enables the current SVA (Shared Virtual Address)
implementation to work in the scalable mode.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Sanjay Kumar
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
---
drivers/iommu/intel-iommu.c | 38
This patch enables the translation for requests without PASID in
the scalable mode by setting up the root and context entries.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Sanjay Kumar
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
---
drivers/iommu/intel-iommu.c
This adds an interface to setup the structures for second
level page table translation type. This includes the types
of second level translation only and pass through.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Sanjay Kumar
Signed-off-by: Lu Baolu
Reviewed-by:
So that they could also be used in other source files.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Kevin Tian
Cc: Liu Yi L
Signed-off-by: Lu Baolu
Reviewed-by: Ashok Raj
---
drivers/iommu/intel-iommu.c | 43 ---
include/linux/intel-iommu.h | 43
In scalable mode, pasid structure is a two level table with
a pasid directory table and a pasid table. Any pasid entry
can be identified by a pasid value in below way.
1
9 6 5 0
.---.---.
| PASID| |
The Intel vt-d spec rev3.0 introduces a new translation
mode called scalable mode, which enables PASID-granular
translations for first level, second level, nested and
pass-through modes. At the same time, the previous
Extended Context (ECS) mode is deprecated (no production
ever implements ECS).
Hi,
Intel vt-d rev3.0 [1] introduces a new translation mode called
'scalable mode', which enables PASID-granular translations for
first level, second level, nested and pass-through modes. The
vt-d scalable mode is the key ingredient to enable Scalable I/O
Virtualization (Scalable IOV) [2] [3],
Hi Joerg,
The graphic guys are looking forward to having this in 4.18.
Is it possible to take it in the following rcs?
Best regards,
Lu Baolu
On 07/08/2018 02:23 PM, Lu Baolu wrote:
> This reverts commit ab96746aaa344fb720a198245a837e266fad3b62.
>
> The commit ab96746aaa34 ("iommu/vt-d: Clean
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