Hi,
On 10/17/18 10:02 AM, Xu Zaibo wrote:
Hi,
On 2018/10/16 9:21, Lu Baolu wrote:
Hi,
On 10/15/2018 04:50 PM, Xu Zaibo wrote:
Hi,
On 2018/10/15 10:48, Lu Baolu wrote:
Hi,
On 10/13/2018 04:25 PM, Xu Zaibo wrote:
Hi,
On 2018/10/12 13:16, Lu Baolu wrote:
Hi,
The Mediate Device is a
Hi,
On 2018/10/16 9:21, Lu Baolu wrote:
Hi,
On 10/15/2018 04:50 PM, Xu Zaibo wrote:
Hi,
On 2018/10/15 10:48, Lu Baolu wrote:
Hi,
On 10/13/2018 04:25 PM, Xu Zaibo wrote:
Hi,
On 2018/10/12 13:16, Lu Baolu wrote:
Hi,
The Mediate Device is a framework for fine-grained physical device
Hi Jean,
On 10/16/18 8:44 PM, Jean-Philippe Brucker wrote:
> On 16/10/2018 10:25, Auger Eric wrote:
>> Hi Jean,
>>
>> On 10/12/18 4:59 PM, Jean-Philippe Brucker wrote:
>>> Implement the virtio-iommu driver, following specification v0.8 [1].
>>> Changes since v2 [2]:
>>>
>>> * Patches 2-4 allow
On 16/10/2018 10:25, Auger Eric wrote:
> Hi Jean,
>
> On 10/12/18 4:59 PM, Jean-Philippe Brucker wrote:
>> Implement the virtio-iommu driver, following specification v0.8 [1].
>> Changes since v2 [2]:
>>
>> * Patches 2-4 allow virtio-iommu to use the PCI transport, since QEMU
>> would like to
On Sun, Oct 14, 2018 at 3:52 AM Christoph Hellwig wrote:
>
> We already build the swiotlb code for 32b-t kernels with PAE support,
> but the code to actually use swiotlb has only been enabled for 64-bit
> kernel for an unknown reason.
>
> Before Linux 4.18 we papers over this fact because the
When we insert the sync sequence number into the CMD_SYNC.MSIData field,
we do so in CPU-native byte order, before writing out the whole command
as explicitly little-endian dwords. Thus on big-endian systems, the SMMU
will receive and write back a byteswapped version of sync_nr, which would
be
On 2018/10/15 20:46, Andrew Murray wrote:
> Hi Zhen,
>
> On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
>> ITS translation register map:
>> 0x-0x003CReserved
>> 0x0040 GITS_TRANSLATER
>> 0x0044-0xFFFCReserved
>>
>> The standard GITS_TRANSLATER
Hi Zhen,
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
> ITS translation register map:
> 0x-0x003C Reserved
> 0x0040GITS_TRANSLATER
> 0x0044-0xFFFC Reserved
>
> The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
> expands the next 4 bytes
On 15/10/18 18:21, Will Deacon wrote:
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
ITS translation register map:
0x-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands
On 2018/10/16 1:21, Will Deacon wrote:
> On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
>> ITS translation register map:
>> 0x-0x003CReserved
>> 0x0040 GITS_TRANSLATER
>> 0x0044-0xFFFCReserved
>>
>> The standard GITS_TRANSLATER register in ITS is
On 2018/10/15 21:52, Robin Murphy wrote:
> On 15/10/18 09:36, Zhen Lei wrote:
>> ITS translation register map:
>> 0x-0x003CReserved
>> 0x0040GITS_TRANSLATER
>> 0x0044-0xFFFCReserved
>>
>> The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
>> expands
Hi Jean,
On 10/12/18 4:59 PM, Jean-Philippe Brucker wrote:
> Implement the virtio-iommu driver, following specification v0.8 [1].
> Changes since v2 [2]:
>
> * Patches 2-4 allow virtio-iommu to use the PCI transport, since QEMU
> would like to phase out the MMIO transport. This produces a
On 2018/10/15 19:17, John Garry wrote:
> On 15/10/2018 09:36, Zhen Lei wrote:
>> ITS translation register map:
>> 0x-0x003CReserved
>> 0x0040GITS_TRANSLATER
>> 0x0044-0xFFFCReserved
>>
>
> Can you add a better opening than the ITS translation register map?
OK
>
>> The
Looked through my personal notes when I played with Intel-IOMMU and
found this useful web-link:
VFIO tips and tricks: "Intel-IOMMU: enabled": It doesn't mean what you
think it means (see [1]).
- Sedat -
[1]
https://vfio.blogspot.com/2016/09/intel-iommu-enabled-it-doesnt-mean-what.html
On Tue, Oct 16, 2018 at 10:03 AM Lu Baolu wrote:
>
> Hi,
>
> On 10/16/18 3:56 PM, Sedat Dilek wrote:
> > On Tue, Oct 16, 2018 at 8:37 AM Lu Baolu wrote:
> >>
> >> Hi Sedat,
> >>
> >> Sorry for late reply.
> >>
> >> Do you still have this issue with newer rc's (like 4.19-rc8)?
> >>
> >> I checked
Hi Robin,
On 10/15/2018 04:00 PM, Robin Murphy wrote:
Hi Hanna,
On 15/10/18 13:00, han...@marvell.com wrote:
From: Hanna Hawa
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit
to ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
Hi,
On 10/16/18 3:56 PM, Sedat Dilek wrote:
On Tue, Oct 16, 2018 at 8:37 AM Lu Baolu wrote:
Hi Sedat,
Sorry for late reply.
Do you still have this issue with newer rc's (like 4.19-rc8)?
I checked the dmesg log you attached there, it seems that the vt-d was
not on actually.
Hi Lu,
On Tue, Oct 16, 2018 at 8:37 AM Lu Baolu wrote:
>
> Hi Sedat,
>
> Sorry for late reply.
>
> Do you still have this issue with newer rc's (like 4.19-rc8)?
>
> I checked the dmesg log you attached there, it seems that the vt-d was
> not on actually.
>
Hi Lu,
Thanks for asking.
I am running a
Hi Sedat,
Sorry for late reply.
Do you still have this issue with newer rc's (like 4.19-rc8)?
I checked the dmesg log you attached there, it seems that the vt-d was
not on actually.
Best regards,
Lu Baolu
On 9/5/18 8:04 PM, Sedat Dilek wrote:
Hi Joerg,
"intel_ioomu=on" was working fine
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