Hi Jacob,
On 12/3/19 4:02 AM, Jacob Pan wrote:
On Fri, 22 Nov 2019 11:04:44 +0800
Lu Baolu wrote:
Intel VT-d 3.0 introduces more caches and interfaces for software to
flush when it runs in the scalable mode. Currently various cache flush
helpers are scattered around. This consolidates them
Hi,
On 12/3/19 7:27 AM, Jacob Pan wrote:
On Thu, 28 Nov 2019 10:25:47 +0800
Lu Baolu wrote:
This adds functions to manipulate first level page tables
which could be used by a scalale mode capable IOMMU unit.
FL and SL page tables are very similar, and I presume we are not using
all the
Hi Jacob,
Thanks for reviewing it.
On 12/3/19 4:19 AM, Jacob Pan wrote:
On Thu, 28 Nov 2019 10:25:42 +0800
Lu Baolu wrote:
Intel VT-d in scalable mode supports two types of page talbes
tables
Got it, thanks!
for DMA translation: the first level page table and the second
level page
Hi,
On 12/3/19 12:13 AM, Jerry Snitselaar wrote:
On Mon Dec 02 19, Jerry Snitselaar wrote:
On Mon Dec 02 19, Lu Baolu wrote:
Hi,
On 12/2/19 2:34 PM, Jerry Snitselaar wrote:
We are seeing DMAR PTE read access not set errors when booting a
kernel with default passthrough, both with a test
On Mon, 25 Nov 2019 07:45:18 +
"Liu, Yi L" wrote:
> Hi Alex,
>
> Thanks for the review. Here I'd like to conclude the major opens in this
> thread and see if we can get some agreements to prepare a new version.
>
> a) IOCTLs for BIND_GPASID and BIND_PROCESS, share a single IOCTL or two
>
On Thu, 28 Nov 2019 10:25:47 +0800
Lu Baolu wrote:
> This adds functions to manipulate first level page tables
> which could be used by a scalale mode capable IOMMU unit.
>
FL and SL page tables are very similar, and I presume we are not using
all the flag bits in FL paging structures for DMA
The pull request you sent on Fri, 29 Nov 2019 13:02:51 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
> tags/iommu-updates-v5.5
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/1daa56bcfd8b329447e0c1b1e91c3925d08489b7
Thank you!
--
On Mon, 2019-12-02 at 11:58 -0800, Jacob Pan wrote:
> Use combined macros for_each_svm_dev() to simplify SVM device iteration
> and error checking.
[]
> diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
[]
> @@ -427,40 +430,36 @@ int intel_svm_unbind_mm(struct device *dev, int
On Thu, 28 Nov 2019 10:25:42 +0800
Lu Baolu wrote:
> Intel VT-d in scalable mode supports two types of page talbes
tables
> for DMA translation: the first level page table and the second
> level page table. The first level page table uses the same
> format as the CPU page table, while the second
On Fri, 22 Nov 2019 11:04:44 +0800
Lu Baolu wrote:
> Intel VT-d 3.0 introduces more caches and interfaces for software to
> flush when it runs in the scalable mode. Currently various cache flush
> helpers are scattered around. This consolidates them by putting them
> in the existing iommu_flush
Mostly extracted from nested SVA/SVM series based on review comments of v7.
https://lkml.org/lkml/2019/10/24/852
This series also adds a few important fixes for native use of SVA. Nested
SVA new code will be submitted separately as a smaller set. Based on the
core branch of IOMMU tree staged for
When setting up first level page tables for sharing with CPU, we need
to ensure IOMMU can support no less than the levels supported by the
CPU.
It is not adequate, as in the current code, to set up 5-level paging
in PASID entry First Level Paging Mode(FLPM) solely based on CPU.
Currently,
Make use of generic IOASID code to manage PASID allocation,
free, and lookup. Replace Intel specific code.
Signed-off-by: Jacob Pan
Reviewed-by: Lu Baolu
Reviewed-by: Eric Auger
Acked-by: Lu Baolu
---
drivers/iommu/Kconfig | 1 +
drivers/iommu/intel-iommu.c | 13 +++--
Add a check during SVM bind to ensure CPU and IOMMU hardware capabilities
are met.
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Acked-by: Lu Baolu
---
drivers/iommu/intel-svm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
Use combined macros for_each_svm_dev() to simplify SVM device iteration
and error checking.
Suggested-by: Andy Shevchenko
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Acked-by: Lu Baolu
---
drivers/iommu/intel-svm.c | 79 +++
1 file changed, 39
Page responses should only be sent when last page in group (LPIG) or
private data is present in the page request. This patch avoids sending
invalid descriptors.
Fixes: 5d308fc1ecf53 ("iommu/vt-d: Add 256-bit invalidation descriptor
support")
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
After each setup for PASID entry, related translation caches must be
flushed. We can combine duplicated code into one function which is less
error prone.
Signed-off-by: Jacob Pan
Reviewed-by: Lu Baolu
Reviewed-by: Eric Auger
Acked-by: Lu Baolu
---
drivers/iommu/intel-pasid.c | 48
PASID allocator uses IDR which is exclusive for the end of the
allocation range. There is no need to decrement pasid_max.
Fixes: af39507305fb ("iommu/vt-d: Apply global PASID in SVA")
Reported-by: Eric Auger
Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Acked-by: Lu Baolu
---
Shared Virtual Memory(SVM) is based on a collective set of hardware
features detected at runtime. There are requirements for matching CPU
and IOMMU capabilities.
The current code checks CPU and IOMMU feature set for SVM support but
the result is never stored nor used. Therefore, SVM can still be
On Mon, 02 Dec 2019 10:22:13 -0800
Joe Perches wrote:
> On Mon, 2019-12-02 at 10:15 -0800, Jacob Pan wrote:
> > On Thu, 21 Nov 2019 13:37:10 -0800
> > Joe Perches wrote:
> >
> > > On Thu, 2019-11-21 at 13:26 -0800, Jacob Pan wrote:
> > > > Use combined macros for_each_svm_dev() to simplify
On Mon, 2019-12-02 at 10:15 -0800, Jacob Pan wrote:
> On Thu, 21 Nov 2019 13:37:10 -0800
> Joe Perches wrote:
>
> > On Thu, 2019-11-21 at 13:26 -0800, Jacob Pan wrote:
> > > Use combined macros for_each_svm_dev() to simplify SVM device
> > > iteration and error checking.
> > []
> > > diff
On Thu, 21 Nov 2019 13:37:10 -0800
Joe Perches wrote:
> On Thu, 2019-11-21 at 13:26 -0800, Jacob Pan wrote:
> > Use combined macros for_each_svm_dev() to simplify SVM device
> > iteration and error checking.
> []
> > diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
> []
> >
On Fri, Nov 29, 2019 at 05:56:55PM +, James Sewart wrote:
> pci_add_dma_alias can now be used to create a dma alias for a range of
> devfns.
>
> Signed-off-by: James Sewart
> ---
> drivers/pci/pci.c| 23 ++-
> drivers/pci/quirks.c | 14 +++---
>
On Fri, Nov 29, 2019 at 05:56:19PM +, James Sewart wrote:
> The number of possible devfns is 256 so the size of the bitmap for
> allocations should be U8_MAX+1.
>
> Signed-off-by: James Sewart
> ---
> drivers/pci/pci.c| 2 +-
> drivers/pci/search.c | 2 +-
> 2 files changed, 2
On Fri, Nov 29, 2019 at 10:21:54PM +0800, Kai-Heng Feng wrote:
> Serious screen flickering when Stoney Ridge outputs to a 4K monitor.
>
> According to Alex Deucher, IOMMU isn't enabled on Windows, so let's do
> the same here to avoid screen flickering on 4K monitor.
Disabling the IOMMU entirely
> + return (mag && mag->size == IOVA_MAG_SIZE);
> + return (!mag || mag->size == 0);
No need for the braces in both cases.
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
I think a subject line better describes what you change, no that
it matches an original algorithm. The fact that the fix matches
the original algorithm can go somewhere towards the commit log,
preferably with a reference to the actual paper.
___
iommu
> -Original Message-
> From: Lucas Stach
> Sent: Sunday, December 1, 2019 7:43 AM
> To: Kai-Heng Feng ; j...@8bytes.org
> Cc: Deucher, Alexander ;
> iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org
> Subject: Re: [PATCH v2] iommu/amd: Disable IOMMU on Stoney Ridge
> systems
On Mon Dec 02 19, Jerry Snitselaar wrote:
On Mon Dec 02 19, Lu Baolu wrote:
Hi,
On 12/2/19 2:34 PM, Jerry Snitselaar wrote:
We are seeing DMAR PTE read access not set errors when booting a
kernel with default passthrough, both with a test kernel and with
a 5.4.0 kernel. Previously we would
> -Original Message-
> From: Christoph Hellwig
> To: David Miller
> Subject: Re: [PATCH v3 0/4] dma-mapping: introduce new dma unmap and sync
> variants
>
> On Wed, Nov 13, 2019 at 12:11:32PM -0800, David Miller wrote:
> > > This series introduces a few new dma unmap and sync api
On 30/11/2019 05:58, Cong Wang wrote:
On Fri, Nov 29, 2019 at 6:43 AM John Garry wrote:
On 29/11/2019 00:48, Cong Wang wrote:
The IOVA cache algorithm implemented in IOMMU code does not
exactly match the original algorithm described in the paper.
which paper?
It's in
On 30/11/2019 06:02, Cong Wang wrote:
On Fri, Nov 29, 2019 at 5:24 AM John Garry wrote:
On 29/11/2019 00:48, Cong Wang wrote:
If the maganize is empty, iova_magazine_free_pfns() should
magazine
Good catch!
be a nop, however it misses the case of mag->size==0. So we
should just call
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