Re: [PATCH 03/10] iommu/ioasid: Introduce per set allocation APIs

Hi Jean, Sorry for the late reply, been trying to redesign the notification part. On Tue, 7 Apr 2020 13:01:07 +0200 Jean-Philippe Brucker wrote: > On Mon, Apr 06, 2020 at 01:02:45PM -0700, Jacob Pan wrote: > > > > + sdata = kzalloc(sizeof(*sdata), GFP_KERNEL); > > > > + if (!sdata)

[PATCH] iomm/arm-smmu: Add stall implementation hook

Add stall implementation hook to enable stalling faults on QCOM platforms which supports it without causing any kind of hardware mishaps. Without this on QCOM platforms, GPU faults can cause unrelated GPU memory accesses to return zeroes. This has the unfortunate result of command-stream reads

[PATCH v12 8/8] iommu/vt-d: Add custom allocator for IOASID

When VT-d driver runs in the guest, PASID allocation must be performed via virtual command interface. This patch registers a custom IOASID allocator which takes precedence over the default XArray based allocator. The resulting IOASID allocation will always come from the host. This ensures that

[PATCH v12 1/8] iommu/vt-d: Move domain helper to header

Move domain helper to header to be used by SVA code. Signed-off-by: Jacob Pan Reviewed-by: Eric Auger Reviewed-by: Kevin Tian --- drivers/iommu/intel-iommu.c | 6 -- include/linux/intel-iommu.h | 6 ++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git

[PATCH v12 2/8] iommu/vt-d: Use a helper function to skip agaw for SL

An Intel iommu domain uses 5-level page table by default. If the iommu that the domain tries to attach supports less page levels, the top level page tables should be skipped. Add a helper to do this so that it could be used in other places. Signed-off-by: Jacob Pan Reviewed-by: Eric Auger ---

[PATCH v12 5/8] iommu/vt-d: Support flushing more translation cache types

When Shared Virtual Memory is exposed to a guest via vIOMMU, scalable IOTLB invalidation may be passed down from outside IOMMU subsystems. This patch adds invalidation functions that can be used for additional translation cache types. Signed-off-by: Jacob Pan Reviewed-by: Eric Auger ---

[PATCH v12 3/8] iommu/vt-d: Add nested translation helper function

Nested translation mode is supported in VT-d 3.0 Spec.CH 3.8. With PASID granular translation type set to 0x11b, translation result from the first level(FL) also subject to a second level(SL) page table translation. This mode is used for SVA virtualization, where FL performs guest virtual to guest

[PATCH v12 7/8] iommu/vt-d: Enlightened PASID allocation

From: Lu Baolu Enabling IOMMU in a guest requires communication with the host driver for certain aspects. Use of PASID ID to enable Shared Virtual Addressing (SVA) requires managing PASID's in the host. VT-d 3.0 spec provides a Virtual Command Register (VCMD) to facilitate this. Writes to this

[PATCH v12 0/8] Nested Shared Virtual Address (SVA) VT-d support

Shared virtual address (SVA), a.k.a, Shared virtual memory (SVM) on Intel platforms allow address space sharing between device DMA and applications. SVA can reduce programming complexity and enhance security. This series is intended to enable SVA virtualization, i.e. enable use of SVA within a

Re: [PATCH] perf/smmuv3: Allow sharing MMIO registers with the SMMU driver

On 2020-04-21 4:57 pm, Jean-Philippe Brucker wrote: Some Arm SMMUv3 implementations, for example Arm CoreLink MMU-600, embed the PMCG registers into the SMMU MMIO regions. It currently causes probe failure because the PMU and SMMU drivers request overlapping resources. Avoid the conflict by

[PATCH] perf/smmuv3: Allow sharing MMIO registers with the SMMU driver

Some Arm SMMUv3 implementations, for example Arm CoreLink MMU-600, embed the PMCG registers into the SMMU MMIO regions. It currently causes probe failure because the PMU and SMMU drivers request overlapping resources. Avoid the conflict by calling devm_ioremap() directly from the PMU driver. We

RE: [PATCH] of_device: removed #include that caused a recursion in included headers

> -Original Message- > From: Rob Herring > Sent: Monday, 20 April 2020 23:37 > > On Mon, Apr 13, 2020 at 04:35:53PM +0300, Hadar Gat wrote: > > Both of_platform.h and of_device.h were included each other. > > In of_device.h, removed unneeded #include to of_platform.h and added > >

Re: [PATCH v5 02/25] iommu/sva: Manage process address spaces

On Mon, Apr 20, 2020 at 11:14:37AM -0700, Fenghua Yu wrote: > > Agreed, perhaps Fenghua can consider that in his patchset. It would > > help align life cycles as well. > > https://lkml.org/lkml/2020/3/30/910> > > Seems we depend on each other: my patch defines pasid in mm_struct. > I can free

RE: [PATCH v2 1/3] iommu/virtio: Add topology description to virtio-iommu config space

> From: Jean-Philippe Brucker > Sent: Saturday, February 29, 2020 1:26 AM > > Platforms without device-tree do not currently have a method for > describing the vIOMMU topology. Provide a topology description embedded > into the virtio device. > > Use PCI FIXUP to probe the config space early,

Re: [PATCH v5] dt-bindings: iommu: renesas, ipmmu-vmsa: convert to json-schema

On Tue, Apr 21, 2020 at 7:16 AM Yoshihiro Shimoda wrote: > Convert Renesas VMSA-Compatible IOMMU bindings documentation > to json-schema. > > Note that original documentation doesn't mention renesas,ipmmu-vmsa > for R-Mobile APE6. But, R-Mobile APE6 is similar to the R-Car > Gen2. So,