Hi Lu,
On 2020-09-11 9:21 p.m., Lu Baolu wrote:
> Tom Murphy has almost done all the work. His latest patch series was
> posted here.
>
> https://lore.kernel.org/linux-iommu/20200903201839.7327-1-murph...@tcd.ie/
>
> Thanks a lot!
>
> This series is a follow-up with below changes:
>
> 1. Add a
Hi Randy,
Thanks for the review.
On Wed, 16 Sep 2020 11:26:00 -0700, Randy Dunlap
wrote:
> On 9/11/20 2:57 PM, Jacob Pan wrote:
> > IOMMU UAPI is newly introduced to support communications between guest
> > virtual IOMMU and host IOMMU. There has been lots of discussions on how
> > it should
The pull request you sent on Fri, 18 Sep 2020 17:10:56 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
> tags/iommu-fixes-v5.9-rc5
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/1fd79656f7d59b2ccfc8d7ec8136db60d21f1e0a
Thank you!
--
Hi Joerg,
On Fri, 18 Sep 2020 12:02:36 +0200, Joerg Roedel wrote:
> Hi Jacob,
>
> On Fri, Sep 11, 2020 at 02:57:49PM -0700, Jacob Pan wrote:
> > IOMMU user API header was introduced to support nested DMA translation
> > and related fault handling. The current UAPI data structures consist of
>
Hi Joerg,
On Fri, 18 Sep 2020 11:44:50 +0200, Joerg Roedel wrote:
> On Fri, Sep 11, 2020 at 02:57:52PM -0700, Jacob Pan wrote:
> > There can be multiple vendor-specific PASID data formats used in UAPI
> > structures. This patch adds enum type with a last entry which makes
> > range checking
On Thu, Sep 17, 2020 at 07:30:41PM +0200, Borislav Petkov wrote:
> On Thu, Sep 17, 2020 at 10:22:39AM -0700, Raj, Ashok wrote:
> > s/translation again/translation
>
> Ok, last one. Now stop looking at that text because you'll find more.
>
> :-)))
Thank you very much for taking care of the
On Mon, Sep 14, 2020 at 11:51 PM Yong Wu wrote:
>
> On Mon, 2020-09-14 at 17:22 -0600, Rob Herring wrote:
> > On Sat, Sep 05, 2020 at 04:08:58PM +0800, Yong Wu wrote:
> > > Convert MediaTek IOMMU to DT schema.
> > >
> > > Signed-off-by: Yong Wu
> > > ---
>
> [...]
>
> > > +properties:
> > > +
Hi
On 18.09.2020 03:13, Yu Kuai wrote:
> if of_find_device_by_node() succeed, exynos_iommu_of_xlate() doesn't have
> a corresponding put_device(). Thus add put_device() to fix the exception
> handling for this function implementation.
>
> Fixes: aa759fd376fb ("iommu/exynos: Add callback for
…
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
…
> @@ -595,6 +597,7 @@ static int qcom_iommu_of_xlate(struct device *dev, struct
> of_phandle_args *args)
>* banks are ok, but multiple devices are not:
>*/
> if (WARN_ON(qcom_iommu !=
On Thu, Sep 10, 2020 at 01:25:38PM +0100, Tom Murphy wrote:
> init_iova_flush_queue can fail if we run out of memory. Fall back to noflush
> queue if it fails.
>
> Signed-off-by: Tom Murphy
> ---
> drivers/iommu/dma-iommu.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
Hi all,
On 24.08.2020 13:40, Marek Szyprowski wrote:
> On 20.08.2020 17:08, Robin Murphy wrote:
>> After 5 years or so of intending to get round to this, finally the
>> time comes! The changes themselves actualy turn out to be relatively
>> mechanical; the bigger concern appears to be how to get
On Fri, Sep 18, 2020 at 04:02:26PM +0100, Robin Murphy wrote:
> On 2020-09-18 15:18, Jean-Philippe Brucker wrote:
> > When building with C=1, sparse reports some issues regarding endianness
> > annotations:
> >
> > arm-smmu-v3.c:221:26: warning: cast to restricted __le64
> > arm-smmu-v3.c:221:24:
Hi Linus,
The following changes since commit 856deb866d16e29bd65952e0289066f6078af773:
Linux 5.9-rc5 (2020-09-13 16:06:00 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
tags/iommu-fixes-v5.9-rc5
for you to fetch changes up to
On 2020-09-18 15:18, Jean-Philippe Brucker wrote:
When building with C=1, sparse reports some issues regarding endianness
annotations:
arm-smmu-v3.c:221:26: warning: cast to restricted __le64
arm-smmu-v3.c:221:24: warning: incorrect type in assignment (different base
types)
On 2020-08-20 13:49, vji...@codeaurora.org wrote:
From: Vijayanand Jitta
When ever an iova alloc request fails we free the iova
ranges present in the percpu iova rcaches and then retry
but the global iova rcache is not freed as a result we could
still see iova alloc failure even after retry as
Hi Robin,
On 20.08.2020 17:08, Robin Murphy wrote:
> Now that arch/arm is wired up for default domains and iommu-dma, we can
> consolidate the shared mapping code onto the generic IOMMU API version,
> and retire the arch-specific implementation.
>
> Signed-off-by: Robin Murphy
>
> ---
> This is
When building with C=1, sparse reports some issues regarding endianness
annotations:
arm-smmu-v3.c:221:26: warning: cast to restricted __le64
arm-smmu-v3.c:221:24: warning: incorrect type in assignment (different base
types)
arm-smmu-v3.c:221:24:expected restricted __le64 [usertype]
On 2020-08-20 13:49, vji...@codeaurora.org wrote:
From: Vijayanand Jitta
When ever a new iova alloc request comes iova is always searched
from the cached node and the nodes which are previous to cached
node. So, even if there is free iova space available in the nodes
which are next to the
On 2020-09-18 09:55, Joerg Roedel wrote:
On Thu, Sep 10, 2020 at 01:25:38PM +0100, Tom Murphy wrote:
init_iova_flush_queue can fail if we run out of memory. Fall back to noflush
queue if it fails.
Signed-off-by: Tom Murphy
---
drivers/iommu/dma-iommu.c | 7 +--
1 file changed, 5
On Fri, 18 Sep 2020 12:18:40 +0200
Jean-Philippe Brucker wrote:
> This is version 10 of the page table sharing support for Arm SMMUv3.
> Patch 1 still needs an Ack from mm maintainers. However patches 4-11 do
> not depend on it, and could get merged for v5.10 regardless.
Hi Jean-Philippe,
It's
On Fri, 18 Sep 2020 12:18:49 +0200
Jean-Philippe Brucker wrote:
> The SMMU has a single ASID space, the union of shared and private ASID
> sets. This means that the SMMU driver competes with the arch allocator
> for ASIDs. Shared ASIDs are those of Linux processes, allocated by the
> arch, and
The invalidate_range() notifier is called for any change to the address
space. Perform the required ATC invalidations.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h| 2 ++
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c| 16 +++-
Let IOASID users take references to existing ioasids with ioasid_get().
ioasid_put() drops a reference and only frees the ioasid when its
reference number is zero. It returns true if the ioasid was freed.
For drivers that don't call ioasid_get(), ioasid_put() is the same as
ioasid_free().
To enable address space sharing with the IOMMU, introduce
arm64_mm_context_get() and arm64_mm_context_put(), that pin down a
context and ensure that it will keep its ASID after a rollover. Export
the symbols to let the modular SMMUv3 driver use them.
Pinning is necessary because a device
From: Fenghua Yu
PASID is shared by all threads in a process. So the logical place to keep
track of it is in the "mm". Both ARM and X86 need to use the PASID in the
"mm".
Suggested-by: Christoph Hellwig
Signed-off-by: Fenghua Yu
Reviewed-by: Tony Luck
---
Let IOMMU drivers allocate a single PASID per mm. Store the mm in the
IOASID set to allow refcounting and searching mm by PASID, when handling
an I/O page fault.
Reviewed-by: Lu Baolu
Signed-off-by: Jean-Philippe Brucker
---
v10: small comment updates
---
drivers/iommu/Kconfig | 5 ++
The sva_bind() function allows devices to access process address spaces
using a PASID (aka SSID).
(1) bind() allocates or gets an existing MMU notifier tied to the
(domain, mm) pair. Each mm gets one PASID.
(2) Any change to the address space calls invalidate_range() which sends
ATC
Aggregate all sanity-checks for sharing CPU page tables with the SMMU
under a single ARM_SMMU_FEAT_SVA bit. For PCIe SVA, users also need to
check FEAT_ATS and FEAT_PRI. For platform SVA, they will have to check
FEAT_STALLS.
Introduce ARM_SMMU_FEAT_BTM (Broadcast TLB Maintenance), but don't
Extract some of the most generic TCR defines, so they can be reused by
the page table sharing code.
Acked-by: Will Deacon
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/io-pgtable-arm.h | 30 ++
drivers/iommu/io-pgtable-arm.c | 27 ++-
The SMMU has a single ASID space, the union of shared and private ASID
sets. This means that the SMMU driver competes with the arch allocator
for ASIDs. Shared ASIDs are those of Linux processes, allocated by the
arch, and contribute in broadcast TLB maintenance. Private ASIDs are
allocated by the
Implement the IOMMU device feature callbacks to support the SVA feature.
At the moment dev_has_feat() returns false since I/O Page Faults and BTM
aren't yet implemented.
Signed-off-by: Jean-Philippe Brucker
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 26 ++
The SMMUv3 driver would like to read the MMFR0 PARANGE field in order to
share CPU page tables with devices. Allow the driver to be built as
module by exporting the read_sanitized_ftr_reg() cpufeature symbol.
Acked-by: Suzuki K Poulose
Signed-off-by: Jean-Philippe Brucker
---
Allow sharing structure definitions with the upcoming SVA support for
Arm SMMUv3, by moving them to a separate header. We could surgically
extract only what is needed but keeping all definitions in one place
looks nicer.
Reviewed-by: Eric Auger
Signed-off-by: Jean-Philippe Brucker
---
With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR,
MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split
into two sets, shared and private. Shared ASIDs correspond to those
obtained from the arch ASID allocator, and private ASIDs are used for
"classic"
This is version 10 of the page table sharing support for Arm SMMUv3.
Patch 1 still needs an Ack from mm maintainers. However patches 4-11 do
not depend on it, and could get merged for v5.10 regardless.
v10:
* Fix patches 3, 8, 9 and 10 following Eric's review.
v9 resend:
Hi Jacob,
On Fri, Sep 11, 2020 at 02:57:49PM -0700, Jacob Pan wrote:
> IOMMU user API header was introduced to support nested DMA translation and
> related fault handling. The current UAPI data structures consist of three
> areas that cover the interactions between host kernel and guest:
> -
On Fri, Sep 11, 2020 at 02:57:52PM -0700, Jacob Pan wrote:
> There can be multiple vendor-specific PASID data formats used in UAPI
> structures. This patch adds enum type with a last entry which makes
> range checking much easier.
But it also makes it much easier to screw up the numbers (which
Hi Suravee,
On Wed, Sep 16, 2020 at 01:55:48PM +, Suravee Suthikulpanit wrote:
> +static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
> +{
> + struct pci_dev *pdev;
> + struct iommu_dev_data *dev_data = NULL;
> + int devid = (event[0] >> EVENT_DEVID_SHIFT) &
On Wed, Sep 16, 2020 at 11:17:20AM +, Suravee Suthikulpanit wrote:
> Commit e52d58d54a32 ("iommu/amd: Use cmpxchg_double() when updating
> 128-bit IRTE") removed an assumption that modify_irte_ga always set
> the valid bit, which requires the callers to set the appropriate value
> for the
On Mon, Sep 14, 2020 at 11:27:48AM +, Wei Liu wrote:
> The IOMMU code needs more work. We're sure for now the IRQ remapping
> hooks are not applicable when Linux is the root.
>
> Signed-off-by: Wei Liu
> ---
> drivers/iommu/hyperv-iommu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1
On Thu, Sep 17, 2020 at 04:31:53AM -0700, Nicolin Chen wrote:
> These two patches fix ACTIVE_TLB_LINES field setting in tegra-smmu
> driver for Tegra210 platforms.
>
> This resend in series groups two previous seperate changes that're
> corelated, being pointed out by Thierry. Also adding his
On Fri, Sep 11, 2020 at 02:53:25PM +0100, Alex Dewar wrote:
> kzfree() is effectively deprecated as of commit 453431a54934 ("mm,
> treewide: rename kzfree() to kfree_sensitive()") and is now simply an
> alias for kfree_sensitive(). So just replace it with kfree_sensitive().
>
> Signed-off-by:
On Thu, Sep 10, 2020 at 01:25:38PM +0100, Tom Murphy wrote:
> init_iova_flush_queue can fail if we run out of memory. Fall back to noflush
> queue if it fails.
>
> Signed-off-by: Tom Murphy
> ---
> drivers/iommu/dma-iommu.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
>
On Sat, Sep 05, 2020 at 03:14:20PM +0800, Wesley Sheng wrote:
> +static void build_pf_iommu_pages(struct iommu_cmd *cmd, u64 address,
> + u16 devid, int pfcnt, bool size,
> + bool inv)
> +{
> + memset(cmd, 0,
On Fri, Sep 11, 2020 at 11:19:12AM +0100, Lad Prabhakar wrote:
> ipmmu-vmsa driver is also used on Renesas RZ/G{1,2} Soc's, update the
> same to reflect the help description for IPMMU_VMSA config.
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Chris Paterson
> ---
> drivers/iommu/Kconfig | 2
On Thu, Sep 10, 2020 at 06:16:21PM +0100, Joao Martins wrote:
> After commit 26e495f34107 ("iommu/amd: Restore IRTE.RemapEn bit after
> programming IRTE"), smatch warns:
>
> drivers/iommu/amd/iommu.c:3870 amd_iommu_deactivate_guest_mode()
> warn: variable dereferenced before check
On Mon, Sep 07, 2020 at 12:16:47PM +0200, Fabien Parent wrote:
> This commit adds IOMMU binding documentation and larb port definitions
> for the MT8167 SoC.
>
> Signed-off-by: Fabien Parent
> Acked-by: Rob Herring
> ---
>
> V4:
> * Added path to mt8167 larb header file
> * Added
On Mon, Sep 14, 2020 at 10:20:55AM +0530, Vijayanand Jitta wrote:
> ping ?
Robin needs to have a look first.
Regards,
Joerg
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Hi All,
I am trying to allocate coherent memory for 33 MB in kerenl driver. and for that i have reserved CMA of 200 MB, but from dmesg, i can see that address reserved for cma is different and what i get with dma_alloc_coherent is different. My pc is x86 machine and tried in different
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