On 06/07/2022 14:00, Tinghan Shen wrote:
> Hi Krzysztof,
>
> After discussing your message with our power team,
> we realized that we need your help to ensure we fully understand you.
>
> On Mon, 2022-07-04 at 14:38 +0200, Krzysztof Kozlowski wrote:
>> On 04/07/2022 1
On 06/07/2022 15:48, Matthias Brugger wrote:
>
>
> On 04/07/2022 14:36, Krzysztof Kozlowski wrote:
>> On 04/07/2022 12:00, Tinghan Shen wrote:
>>> The max clock items for the dts node with compatible
>>> 'mediatek,mt8195-smi-sub-common' should be 3.
>>>
On 06/07/2022 15:41, Matthias Brugger wrote:
>
>
> On 04/07/2022 14:38, Krzysztof Kozlowski wrote:
>> On 04/07/2022 12:00, Tinghan Shen wrote:
>>> Add power domains controller node for mt8195.
>>>
>>> Signed-off-by: Weiyi Lu
>>> Signed-off-
On 04/07/2022 12:00, Tinghan Shen wrote:
> From: "Jason-JH.Lin"
>
> Add display node for vdosys0 of mt8195.
>
> Signed-off-by: Jason-JH.Lin
> Signed-off-by: Tinghan Shen
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
> 1 file changed, 109 insertions(+)
>
>
On 04/07/2022 12:00, Tinghan Shen wrote:
> Add power domains controller node for mt8195.
>
> Signed-off-by: Weiyi Lu
> Signed-off-by: Tinghan Shen
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 327 +++
> 1 file changed, 327 insertions(+)
>
> diff --git
On 04/07/2022 12:00, Tinghan Shen wrote:
> The max clock items for the dts node with compatible
> 'mediatek,mt8195-smi-sub-common' should be 3.
>
> However, the dtbs_check of such node will get following message,
> arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: smi@1401: clock-names:
> ['apb',
On 02/07/2022 23:37, Sam Protsenko wrote:
> SysMMU v7 might have different register layouts (VM capable or non-VM
> capable). Check which layout is implemented in current SysMMU module and
> prepare the corresponding register table for futher usage. This way is
> faster and more elegant than
On 02/07/2022 23:37, Sam Protsenko wrote:
> SysMMU v7 can have Virtual Machine registers, which implement multiple
> translation domains. The driver should know if it's true or not, as VM
> registers shouldn't be accessed if not present. Read corresponding
> capabilities register to obtain that
On 02/07/2022 23:37, Sam Protsenko wrote:
> SysMMU v5+ supports 36 bit physical address space. Set corresponding DMA
> mask to avoid falling back to SWTLBIO usage in dma_map_single() because
> of failed dma_capable() check.
>
> The original code for this fix was suggested by Marek.
>
>
because Exynos based boards I have doesn't boot with non-4KB
> page size for other reasons.
> ---
> drivers/iommu/exynos-iommu.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
___
On 30/05/2022 23:00, Oleksandr Tyshchenko wrote:
> From: Oleksandr Tyshchenko
Thank you for your patch. There is something to discuss/improve.
> diff --git a/Documentation/devicetree/bindings/iommu/xen,grant-dma.yaml
> b/Documentation/devicetree/bindings/iommu/xen,grant-dma.yaml
> new file
On 17/05/2022 15:21, AngeloGioacchino Del Regno wrote:
> Add property "mediatek,pericfg" to let the mtk_iommu driver retrieve
> a phandle to the pericfg syscon instead of performing a per-soc
> compatible lookup, as it was also done with infracfg.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
On 17/05/2022 15:21, AngeloGioacchino Del Regno wrote:
> Add property "mediatek,infracfg" to let the mtk_iommu driver retrieve
> a phandle to the infracfg syscon instead of performing a per-soc
> compatible lookup.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
>
On 03/05/2022 18:34, Bjorn Andersson wrote:
> Add compatible for the Qualcomm SC8280XP platform to the ARM SMMU
> DeviceTree binding.
>
> Signed-off-by: Bjorn Andersson
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On 02/05/2022 15:34, Geert Uytterhoeven wrote:
> Despite the name, R-Car V3U is the first member of the R-Car Gen4
> family. Hence move its compatible value to the R-Car Gen4 section.
>
Acked-by: Krzysztof Kozlowski
Best regards,
On 02/05/2022 15:34, Geert Uytterhoeven wrote:
> Despite the name, R-Car V3U is the first member of the R-Car Gen4
> family. Hence move its compatible value to the R-Car Gen4 section.
>
> Signed-off-by: Geert Uytterhoeven
Acked-by: Krzysztof Kozlowski
Best regard
dmac.yaml | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On 02/05/2022 15:34, Geert Uytterhoeven wrote:
> Despite the name, R-Car V3U is the first member of the R-Car Gen4
> family. Hence move its compatible value to the R-Car Gen4 section.
>
> Signed-off-by: Geert Uytterhoeven
Acked-by: Krzysztof Kozlowski
Best regard
On 02/05/2022 15:34, Geert Uytterhoeven wrote:
> Despite the name, R-Car V3U is the first member of the R-Car Gen4
> family. Hence move its compatible value to the R-Car Gen4 section.
>
> Signed-off-by: Geert Uytterhoeven
Acked-by: Krzysztof Kozlowski
Best regard
Car Gen3 SoC.
>
> Hence move its compatible value to the R-Car Gen4 section.
>
> Signed-off-by: Geert Uytterhoeven
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On 02/05/2022 15:34, Geert Uytterhoeven wrote:
> Despite the name, R-Car V3U is the first member of the R-Car Gen4
> family. Hence move its compatible value to the R-Car Gen4 section.
>
> Signed-off-by: Geert Uytterhoeven
Acked-by: Krzysztof Kozlowski
Best regard
On 02/05/2022 10:37, Rohit Agarwal wrote:
> Add devicetree binding for Qualcomm SDX65 SMMU.
>
> Signed-off-by: Rohit Agarwal
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On 28/04/2022 11:23, Robin Murphy wrote:
> On 2022-04-28 07:56, Krzysztof Kozlowski wrote:
>> On 27/04/2022 13:25, Andre Przywara wrote:
>>> The Page Request Interface (PRI) is an optional PCIe feature. As such, a
>>> SMMU would not need to handle it if the PCIe host br
On 28/04/2022 03:03, Samuel Holland wrote:
Thank you for your patch. There is something to discuss/improve.
> +
> +if:
> + properties:
> +compatible:
> + contains:
> +enum:
> + - allwinner,sun50i-h6-iommu
> +
> +then:
> + required:
> +- resets
else:
properties:
On 27/04/2022 13:25, Andre Przywara wrote:
> The Page Request Interface (PRI) is an optional PCIe feature. As such, a
> SMMU would not need to handle it if the PCIe host bridge or the SMMU
> itself do not implement it. Also an SMMU could be connected to a platform
> device, without any PRI
.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Krzysztof Kozlowski
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Krzysztof
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On 11/04/2022 11:50, Rohit Agarwal wrote:
> Add devicetree binding for Qualcomm SDX65 SMMU.
>
> Signed-off-by: Rohit Agarwal
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Krzysztof Kozlowski
Be
daf
[7/7] memory: mtk-smi: mt8186: Add smi support
commit: 86a010bfc73983aa8cd914f1e5f73962b0406678
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--
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> 2 files changed, 221 insertions(+)
> create mode 100644 include/dt-bindings/memory/mt8186-memory-port.h
>
Acked-by: Krzysztof Kozlowski
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Krzysztof
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On 20/01/2022 21:19, Sam Protsenko wrote:
> Introduce new driver for modern Exynos ARMv8 SoCs, e.g. Exynos850. Also
> it's used for Google's GS101 SoC.
>
> This is squashed commit, contains next patches of different authors. See
> `iommu-exynos850-dev' branch for details: [1].
>
> Original
On 20/01/2022 21:19, Sam Protsenko wrote:
> This is a draft of a new IOMMU driver used in modern Exynos SoCs (like
> Exynos850) and Google's GS101 SoC (used in Pixel 6 phone). Most of its
> code were taken from GS101 downstream kernel [1], with some extra
> patches on top (fixes from Exynos850
On 20/01/2022 21:19, Sam Protsenko wrote:
> Only example of usage and header for now.
>
> Signed-off-by: Sam Protsenko
> ---
> .../bindings/iommu/samsung,sysmmu-v8.txt | 31 +
Please, don't copy paste bindings or entire drviers from vendor kernel.
It looks very bad. Instead,
1st arg cell
> - description: 2nd arg cell
>
> With this change, some examples need updating so that the bracketing of
> property values matches the schema.
>
Samsung and memory controller bits look good:
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
_
On 13/01/2022 12:10, Yong Wu wrote:
> Function clk_bulk_prepare_enable() returns 0 for success or a negative
> number for error. Fix this code style issue.
The message does not really make sense. If negative is returned, then
the check (ret < 0) was correct.
I guess you wanted to say that common
On 11/01/2022 07:39, Yong Wu wrote:
> Sleep control means that when the larb goes to sleep, we should wait a bit
> until all the current commands are finished. Thus, when the larb runtime
> suspends, we need to enable this function to wait until all the existed
> commands are finished. When the
On 11/01/2022 07:39, Yong Wu wrote:
> The successful return value for clk_bulk_prepare_enable is 0, rather than
> "< 0". Fix this.
I do not understand. The commit description does not match the code.
What is the error here?
>
> Fixes: 0e14917c57f9 ("memory: mtk-smi: Use clk_bulk clock ops")
On 11/01/2022 07:39, Yong Wu wrote:
> Mute the warning from "make dtbs_check":
>
> larb@14017000: clock-names: ['apb', 'smi'] is too short
> arch/arm64/boot/dts/mediatek/mt8183-evb.dt.yaml
> arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dt.yaml
> ...
>
>
On 11/01/2022 07:38, Yong Wu wrote:
> Mute the warning from "make dtbs_check":
>
> larb@14016000: 'mediatek,larb-id' is a required property
> arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dt.yaml
> larb@15001000: 'mediatek,larb-id' is a required property
>
On 03/12/2021 07:40, Yong Wu wrote:
> sleep control means that when the larb go to sleep, we should wait a bit
s/go/goes/
> until all the current commands are finished. thus, when the larb runtime
Please start every sentence with a capital letter.
> suspend, we need enable this function to
t; __rpm_callback+0x44/0x150
> rpm_callback+0x6c/0x78
> rpm_resume+0x310/0x558
> __pm_runtime_resume+0x3c/0x88
>
> [...]
Applied, thanks!
[1/1] memory: mtk-smi: Fix a null dereference for the ostd
commit: 8c5ba21c16bd7f8e23b
On 01/11/2021 07:09, Yong Wu wrote:
> On Fri, 2021-10-29 at 19:35 +0200, Krzysztof Kozlowski wrote:
>> On 28/10/2021 07:50, Yong Wu wrote:
>>> We add the ostd setting for mt8195. It introduces a abort for the
>>> previous SoC which doesn't have ostd setting. This
On 28/10/2021 07:50, Yong Wu wrote:
> We add the ostd setting for mt8195. It introduces a abort for the
> previous SoC which doesn't have ostd setting. This is the log:
>
> Unable to handle kernel NULL pointer dereference at virtual address
> 0080
> ...
> pc :
On 15/10/2021 15:38, AngeloGioacchino Del Regno wrote:
>> Use clk_bulk interface instead of the orginal one to simplify the code.
>>
>> For SMI larbs: Require apb/smi clocks while gals is optional.
>> For SMI common: Require apb/smi/gals0/gal1 in has_gals case. Otherwise,
>> also
commit: 93403ede5aa4edeec2c63541b185d9c4fc9ae1e4
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--
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On 10/08/2021 10:08, Yong Wu wrote:
> This patchset mainly adds SMI support for mt8195.
>
> Comparing with the previous version, add two new functions:
> a) add smi sub common
> b) add initial setting for smi-common and smi-larb.
>
> Change note:
> v3:1) In the dt-binding:
>a. Change
On Tue, 13 Jul 2021 at 10:27, Krzysztof Kozlowski
wrote:
>
> On Mon, 12 Jul 2021 at 16:14, Rob Herring wrote:
> >
> > On Tue, Jun 22, 2021 at 11:56 PM Krzysztof Kozlowski
> > wrote:
> > >
> > > On Mon, 21 Jun 2021 16:00:36 +0200, Thierry Reding wrote:
On Mon, 12 Jul 2021 at 16:14, Rob Herring wrote:
>
> On Tue, Jun 22, 2021 at 11:56 PM Krzysztof Kozlowski
> wrote:
> >
> > On Mon, 21 Jun 2021 16:00:36 +0200, Thierry Reding wrote:
> > > Commit 4287861dca9d ("dt-bindings: arm-smmu: Add Tegra186 compatible
>
On 11/07/2021 10:29, Yong Wu wrote:
> On Thu, 2021-07-08 at 11:32 +0200, Krzysztof Kozlowski wrote:
>> On 16/06/2021 13:43, Yong Wu wrote:
>>> smi have many clocks: apb/smi/gals.
>>> This patch use clk_bulk interface instead of the orginal one to simply
>>> th
On 16/06/2021 13:43, Yong Wu wrote:
> This patch adds smi-sub-common support. some larbs may connect with the
> smi-sub-common, then connect with smi-common.
Please start sentences with capital letter. This (similarly to "This
patch") appears in multiple patches.
>
> Before we create device
On 16/06/2021 13:43, Yong Wu wrote:
> This is a preparing patch for adding smi sub common.
Don't write "This patch". Use simple imperative:
"Prepare for adding smi sub common."
https://elixir.bootlin.com/linux/v5.13/source/Documentation/process/submitting-patches.rst#L89
> About the previou
On 16/06/2021 13:43, Yong Wu wrote:
> smi have many clocks: apb/smi/gals.
> This patch use clk_bulk interface instead of the orginal one to simply
> the code.
>
> gals is optional clk(some larbs may don't have gals). use clk_bulk_optional
> instead. and then remove the has_gals flag.
>
> Also
On 16/06/2021 13:43, Yong Wu wrote:
> This patch adds mt8195 smi supporting in the bindings.
>
> In mt8195, there are two smi-common HW, one is for vdo(video output),
> the other is for vpp(video processing pipe). They connects with different
> smi-larbs, then some setting(bus_sel) is different.
3 files changed, 33 insertions(+), 1 deletion(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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derstand this will go through IOMMU tree. Do you know about any
further patches for memory controllers which will need the header?
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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json-schema syntax
commit: bf3ec9deaa33889630722c47f7bb86ba58872ea7
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--
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On 18/06/2021 21:47, Rob Herring wrote:
> On Thu, Jun 3, 2021 at 10:49 AM Thierry Reding
> wrote:
>>
>> From: Thierry Reding
>>
>> The ARM SMMU instantiations found on Tegra186 and later need inter-
>> operation with the memory controller in order to correctly program
>> stream ID overrides.
>>
8cb4ef1
[6/9] iommu/arm-smmu: Use Tegra implementation on Tegra186
commit: 2c1bc371268862a991a6498e1dddc8971b9076b8
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On 10/06/2021 19:29, Will Deacon wrote:
> On Thu, Jun 10, 2021 at 05:05:27PM +0200, Thierry Reding wrote:
>> On Thu, Jun 10, 2021 at 04:23:56PM +0200, Krzysztof Kozlowski wrote:
>>> On 10/06/2021 11:19, Thierry Reding wrote:
>>>> On Tue, Jun 08, 2021 at 05:48:51PM +01
On 10/06/2021 11:19, Thierry Reding wrote:
> On Tue, Jun 08, 2021 at 05:48:51PM +0100, Will Deacon wrote:
>> On Tue, Jun 08, 2021 at 04:38:48PM +0200, Thierry Reding wrote:
>>> On Tue, Jun 08, 2021 at 01:01:29PM +0100, Will Deacon wrote:
>>>> On Mon, Jun 07, 2021
On 07/06/2021 10:49, Krzysztof Kozlowski wrote:
> Hi Olof and Arnd,
>
> Tegra memory controller driver changes with necessary dependency from Thierry
> (which you will also get from him):
> 1. Dmitry's power domain work on Tegra MC drivers,
> 2. Necessary clock and regu
le testing for all drivers
memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table()
memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table()
Krzysztof Kozlowski (1):
Merge tag 'tegra-for-5.14-memory' of
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into
for-v5.1
d pushes the code to
> deal with the Tegra-specific programming into the NVIDIA SMMU
> implementation.
>
> [...]
Applied, thanks!
[1/9] memory: tegra: Implement SID override programming
commit: 393d66fd2cacba3e6aa95d7bb38790bfb7b1cc3a
On 02/06/2021 16:58, Thierry Reding wrote:
> On Wed, Jun 02, 2021 at 12:40:49PM +0100, Will Deacon wrote:
>> On Wed, Jun 02, 2021 at 12:44:58PM +0200, Krzysztof Kozlowski wrote:
>>> On 02/06/2021 10:52, Thierry Reding wrote:
>>>> On Wed, Jun 02, 2021 at 09:35:13AM +0
On 02/06/2021 16:53, Thierry Reding wrote:
> On Wed, Jun 02, 2021 at 12:44:58PM +0200, Krzysztof Kozlowski wrote:
>> On 02/06/2021 10:52, Thierry Reding wrote:
>>> On Wed, Jun 02, 2021 at 09:35:13AM +0200, Krzysztof Kozlowski wrote:
>>>> On 02/06/2021 09:33, Krzyszto
On 02/06/2021 10:52, Thierry Reding wrote:
> On Wed, Jun 02, 2021 at 09:35:13AM +0200, Krzysztof Kozlowski wrote:
>> On 02/06/2021 09:33, Krzysztof Kozlowski wrote:
>>> On 01/06/2021 20:08, Thierry Reding wrote:
>>>> On Tue, Jun 01, 2021 at 01:26:46PM +0100, Will Deac
On 02/06/2021 09:33, Krzysztof Kozlowski wrote:
> On 01/06/2021 20:08, Thierry Reding wrote:
>> On Tue, Jun 01, 2021 at 01:26:46PM +0100, Will Deacon wrote:
>>> On Fri, May 28, 2021 at 07:05:28PM +0200, Thierry Reding wrote:
>>>> On Tue, Apr 20, 2021 at 07:26:09
On 01/06/2021 20:08, Thierry Reding wrote:
> On Tue, Jun 01, 2021 at 01:26:46PM +0100, Will Deacon wrote:
>> On Fri, May 28, 2021 at 07:05:28PM +0200, Thierry Reding wrote:
>>> On Tue, Apr 20, 2021 at 07:26:09PM +0200, Thierry Reding wrote:
From: Thierry Reding
Hi,
this
On 26/04/2021 14:13, Thierry Reding wrote:
> On Mon, Apr 26, 2021 at 10:28:43AM +0200, Krzysztof Kozlowski wrote:
(...)
>>> +
>>> + value = readl(mc->regs + client->regs.sid.override);
>>> + old = value & MC_SID_STREAMID_OVERRIDE_MASK;
>>> +
On 20/04/2021 19:26, Thierry Reding wrote:
> From: Thierry Reding
>
> Instead of programming all SID overrides during early boot, perform the
> operation on-demand after the SMMU translations have been set up for a
> device. This reuses data from device tree to match memory clients for a
>
venc
>
> [...]
Applied, thanks!
[04/16] memory: mtk-smi: Add device-link between smi-larb and smi-common
commit: 6ce2c05b21189eb17b3aa26720cc5841acf9dce8
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--
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On 13/04/2021 08:04, Yong Wu wrote:
> On Sat, 2021-04-10 at 14:40 +0200, Krzysztof Kozlowski wrote:
>> On 10/04/2021 11:11, Yong Wu wrote:
>>> Normally, If the smi-larb HW need work, we should enable the smi-common
>>> HW power and clock firstly.
>>> This pa
ong Wu
> Reviewed-by: Evan Green
> ---
> drivers/memory/mtk-smi.c | 14 --
> include/soc/mediatek/smi.h | 20
> 2 files changed, 34 deletions(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
-
> 1 file changed, 10 insertions(+), 9 deletions(-)
I understood this is a dependency for other patches, so:
Acked-by: Krzysztof Kozlowski
If I am wrong and I can take it via memory tree, let me know.
Best regards,
Krzysztof
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The initialization of 'fault_addr' local variable is not needed as it is
shortly after overwritten.
Addresses-Coverity: Unused value
Signed-off-by: Krzysztof Kozlowski
---
drivers/iommu/exynos-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/exynos
On Tue, Jan 26, 2021 at 02:00:55PM +0800, Yong Wu wrote:
> This patch mainly support SMI modular. Switch MTK_SMI to tristate,
> and add module_exit/module_license.
>
> Signed-off-by: Yong Wu
> ---
> This patch rebase on the clean v5.11-rc1.
> and this one: memory: mtk-smi: Use
On Mon, Jan 25, 2021 at 05:28:05PM +0800, Yong Wu wrote:
> On Mon, 2021-01-25 at 09:40 +0100, Krzysztof Kozlowski wrote:
> > On Mon, Jan 25, 2021 at 02:49:41PM +0800, Yong Wu wrote:
> > > On Fri, 2021-01-22 at 22:34 +0100, Krzysztof Kozlowski wrote:
> > > > On Thu, Ja
On Mon, Jan 25, 2021 at 02:49:44PM +0800, Yong Wu wrote:
> On Fri, 2021-01-22 at 22:35 +0100, Krzysztof Kozlowski wrote:
> > On Thu, Jan 21, 2021 at 02:24:29PM +0800, Yong Wu wrote:
> > > This patch switches MTK_SMI to tristate. Support it could be 'm'.
> > >
> &g
On Mon, Jan 25, 2021 at 02:49:41PM +0800, Yong Wu wrote:
> On Fri, 2021-01-22 at 22:34 +0100, Krzysztof Kozlowski wrote:
> > On Thu, Jan 21, 2021 at 02:24:28PM +0800, Yong Wu wrote:
> > > The config MTK_SMI always depends on MTK_IOMMU which is built-in
> > > cu
On Thu, Jan 21, 2021 at 02:24:29PM +0800, Yong Wu wrote:
> This patch switches MTK_SMI to tristate. Support it could be 'm'.
>
> Meanwhile, Fix a build issue while MTK_SMI is built as module.
s/Fix/fix.
What error is being fixed here? How can I reproduce it? Aren't you just
adjusting it to
On Thu, Jan 21, 2021 at 02:24:28PM +0800, Yong Wu wrote:
> The config MTK_SMI always depends on MTK_IOMMU which is built-in
> currently. Thus we don't have module_exit before. This patch adds
> module_exit and module_license. It is a preparing patch for supporting
> MTK_SMI could been built as a
On Thu, Jan 21, 2021 at 02:24:27PM +0800, Yong Wu wrote:
> In this file, we have 2 drivers, smi-common and smi-larb.
> Use platform_register_drivers.
>
> Signed-off-by: Yong Wu
> ---
> drivers/memory/mtk-smi.c | 25 ++---
> 1 file changed, 6 insertions(+), 19 deletions(-)
djust its bank number.
>
> Each a bank is a iova_region which is a independent iommu-domain.
> the iova range for each iommu-domain can't cross 4G.
>
> Signed-off-by: Yong Wu
> Acked-by: Krzysztof Kozlowski # memory part
> ---
> drivers/iommu/mtk_iommu.c | 12 +++
e/soc/mediatek/smi.h | 2 --
> 4 files changed, 2 insertions(+), 9 deletions(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On Wed, Nov 11, 2020 at 08:38:19PM +0800, Yong Wu wrote:
> This patch adds decriptions for mt8192 IOMMU and SMI.
>
> mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> table format. The M4U-SMI HW diagram is as below:
>
> EMI
>
e in its special
> range.
>
> This is a preparing patch for multi-domain support.
>
> Signed-off-by: Yong Wu
> ---
> include/dt-bindings/memory/mtk-smi-larb-port.h | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
Acke
ndings/memory/mtk-smi-larb-port.h | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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ings/memory/mtk-smi-larb-port.h | 15 +++
> 6 files changed, 20 insertions(+), 5 deletions(-)
> create mode 100644 include/dt-bindings/memory/mtk-smi-larb-port.h
>
> diff --git a/include/dt-bindings/memory/mt2712-larb-port.h
> b/include/dt-bindings/memory/mt2712-larb-p
On Tue, Nov 03, 2020 at 01:42:00PM +0800, Yong Wu wrote:
> Add mt8192 smi support.
>
> Signed-off-by: Yong Wu
> ---
> drivers/memory/mtk-smi.c | 19 +++
Thanks, applied.
Best regards,
Krzysztof
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On Tue, Nov 03, 2020 at 01:41:58PM +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
>
> Signed-off-by: Yong Wu
> ---
> .../mediatek,smi-common.txt | 50 ---
> .../mediatek,smi-common.yaml | 140 ++
>
On Tue, Nov 03, 2020 at 01:41:59PM +0800, Yong Wu wrote:
> Add mt8192 smi support in the bindings.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Rob Herring
> ---
> .../bindings/memory-controllers/mediatek,smi-common.yaml | 4 +++-
> .../bindings/memory-controllers/mediatek,smi-larb.yaml
On Mon, 2 Nov 2020 at 06:31, Yong Wu wrote:
>
> On Sat, 2020-10-31 at 12:36 +0100, Krzysztof Kozlowski wrote:
> > On Fri, Oct 30, 2020 at 05:12:52PM +0800, Yong Wu wrote:
> > > Convert MediaTek SMI to DT schema.
> > >
> > > CC: Fabien Parent
> > &g
On Fri, Oct 30, 2020 at 05:12:52PM +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
>
> CC: Fabien Parent
> CC: Ming-Fan Chen
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
> ---
> .../mediatek,smi-common.txt | 50 ---
> .../mediatek,smi-common.yaml
On Wed, Sep 30, 2020 at 03:06:23PM +0800, Yong Wu wrote:
> This patch mainly adds support for mt8192 IOMMU and SMI.
>
> mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> table format. The M4U-SMI HW diagram is as below:
>
> EMI
>
On Tue, 6 Oct 2020 at 06:27, Yong Wu wrote:
>
> On Fri, 2020-10-02 at 13:07 +0200, Krzysztof Kozlowski wrote:
> > On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > > Convert MediaTek IOMMU to DT schema.
> > >
> > > Signed-off-by: Yong Wu
>
On Mon, 12 Oct 2020 at 14:02, Yong Wu wrote:
>
> On Mon, 2020-10-12 at 09:18 +0200, Krzysztof Kozlowski wrote:
> > On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> > > On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> > > > On Tue, 6
On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> > On Tue, 6 Oct 2020 at 06:27, Yong Wu wrote:
> > >
> > > On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > > > On Wed,
On Tue, Oct 06, 2020 at 12:26:45PM +0800, Yong Wu wrote:
> Hi Krzysztof,
>
> On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote:
> > On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote:
> > > This patch adds decriptions for mt8192 IOMMU and SMI.
> > >
+++
> include/soc/mediatek/smi.h | 1 +
> 3 files changed, 17 insertions(+), 3 deletions(-)
For the memory part:
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
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On Tue, 6 Oct 2020 at 06:27, Yong Wu wrote:
>
> On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > Convert MediaTek SMI to DT schema.
> > >
> > > Signed-off-by: Yong Wu
>
On Wed, Sep 30, 2020 at 03:06:47PM +0800, Yong Wu wrote:
> Add mt8192 smi support.
>
> Signed-off-by: Yong Wu
> ---
> drivers/memory/mtk-smi.c | 19 +++
> 1 file changed, 19 insertions(+)
Does it depend on any of the previous patches (so can it be applied
independently)?
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