Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2019-01-01 Thread Vivek Gautam
Hi Robin, On Fri, Dec 7, 2018 at 2:54 PM Vivek Gautam wrote: > > Hi Robin, > > On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote: > > > > On 04/12/2018 11:01, Vivek Gautam wrote: > > > Qualcomm SoCs have an additional level of cache called as > > > System cache, aka. Last level cache (LLC).

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2019-01-01 Thread Vivek Gautam
On Thu, Dec 13, 2018 at 9:20 AM Tomasz Figa wrote: > > On Fri, Dec 7, 2018 at 6:25 PM Vivek Gautam > wrote: > > > > Hi Robin, > > > > On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote: > > > > > > On 04/12/2018 11:01, Vivek Gautam wrote: > > > > Qualcomm SoCs have an additional level of cache

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-12-12 Thread Tomasz Figa
On Fri, Dec 7, 2018 at 6:25 PM Vivek Gautam wrote: > > Hi Robin, > > On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote: > > > > On 04/12/2018 11:01, Vivek Gautam wrote: > > > Qualcomm SoCs have an additional level of cache called as > > > System cache, aka. Last level cache (LLC). This cache

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-12-07 Thread Vivek Gautam
Hi Robin, On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote: > > On 04/12/2018 11:01, Vivek Gautam wrote: > > Qualcomm SoCs have an additional level of cache called as > > System cache, aka. Last level cache (LLC). This cache sits right > > before the DDR, and is tightly coupled with the memory

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-12-04 Thread Robin Murphy
On 04/12/2018 11:01, Vivek Gautam wrote: Qualcomm SoCs have an additional level of cache called as System cache, aka. Last level cache (LLC). This cache sits right before the DDR, and is tightly coupled with the memory controller. The cache is available to all the clients present in the SoC

[PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-12-04 Thread Vivek Gautam
Qualcomm SoCs have an additional level of cache called as System cache, aka. Last level cache (LLC). This cache sits right before the DDR, and is tightly coupled with the memory controller. The cache is available to all the clients present in the SoC system. The clients request their slices from

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-10-24 Thread Vivek Gautam
Hi Tomasz, On Tue, Oct 23, 2018 at 9:45 AM Tomasz Figa wrote: > > Hi Vivek, > > On Fri, Jun 15, 2018 at 7:53 PM Vivek Gautam > wrote: > > > > Qualcomm SoCs have an additional level of cache called as > > System cache or Last level cache[1]. This cache sits right > > before the DDR, and is

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-10-22 Thread Tomasz Figa
Hi Vivek, On Fri, Jun 15, 2018 at 7:53 PM Vivek Gautam wrote: > > Qualcomm SoCs have an additional level of cache called as > System cache or Last level cache[1]. This cache sits right > before the DDR, and is tightly coupled with the memory > controller. > The cache is available to all the

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-10-04 Thread Vivek Gautam
Hi Will, On Fri, Sep 28, 2018 at 6:49 PM Will Deacon wrote: > > Hi Vivek, > > On Thu, Sep 20, 2018 at 05:11:53PM +0530, Vivek Gautam wrote: > > On Wed, Jun 27, 2018 at 10:07 PM Will Deacon wrote: > > > On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: > > > > On Fri, Jun 15, 2018 at

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-09-28 Thread Will Deacon
Hi Vivek, On Thu, Sep 20, 2018 at 05:11:53PM +0530, Vivek Gautam wrote: > On Wed, Jun 27, 2018 at 10:07 PM Will Deacon wrote: > > On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: > > > On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon wrote: > > > > On Fri, Jun 15, 2018 at 04:23:29PM

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-09-20 Thread Vivek Gautam
Hi Will, On Wed, Jun 27, 2018 at 10:07 PM Will Deacon wrote: > > Hi Vivek, > > On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: > > On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon wrote: > > > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote: > > >> Qualcomm SoCs have an

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-09-20 Thread Vivek Gautam
On Thu, Sep 20, 2018 at 1:05 AM Jordan Crouse wrote: > > On Tue, Jul 24, 2018 at 03:13:37PM +0530, Vivek Gautam wrote: > > Hi Will, > > > > > > On Wed, Jun 27, 2018 at 10:07 PM, Will Deacon wrote: > > > Hi Vivek, > > > > > > On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: > > >> On

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-09-19 Thread Jordan Crouse
On Tue, Jul 24, 2018 at 03:13:37PM +0530, Vivek Gautam wrote: > Hi Will, > > > On Wed, Jun 27, 2018 at 10:07 PM, Will Deacon wrote: > > Hi Vivek, > > > > On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: > >> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon wrote: > >> > On Fri, Jun

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-07-24 Thread Vivek Gautam
Hi Will, On Wed, Jun 27, 2018 at 10:07 PM, Will Deacon wrote: > Hi Vivek, > > On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: >> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon wrote: >> > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote: >> >> Qualcomm SoCs have an

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-06-19 Thread Vivek Gautam
Hi Will, On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon wrote: > Hi Vivek, > > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote: >> Qualcomm SoCs have an additional level of cache called as >> System cache or Last level cache[1]. This cache sits right >> before the DDR, and is

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-06-15 Thread Jordan Crouse
On Fri, Jun 15, 2018 at 05:52:32PM +0100, Will Deacon wrote: > Hi Vivek, > > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote: > > Qualcomm SoCs have an additional level of cache called as > > System cache or Last level cache[1]. This cache sits right > > before the DDR, and is

Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-06-15 Thread Will Deacon
Hi Vivek, On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote: > Qualcomm SoCs have an additional level of cache called as > System cache or Last level cache[1]. This cache sits right > before the DDR, and is tightly coupled with the memory > controller. > The cache is available to all

[PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache

2018-06-15 Thread Vivek Gautam
Qualcomm SoCs have an additional level of cache called as System cache or Last level cache[1]. This cache sits right before the DDR, and is tightly coupled with the memory controller. The cache is available to all the clients present in the SoC system. The clients request their slices from this