Re: [PATCH 1/1] iommu/arm-smmu-v3: replace writel with writel_relaxed in queue_inc_prod

On 2017/6/20 19:35, Robin Murphy wrote: > On 20/06/17 12:04, Zhen Lei wrote: >> This function is protected by spinlock, and the latter will do memory >> barrier implicitly. So that we can safely use writel_relaxed. In fact, the >> dmb operation will lengthen the time protected by lock, which

Re: [PATCH v7 07/36] x86/mm: Don't use phys_to_virt in ioremap() if SME is active

On Fri, 16 Jun 2017, Tom Lendacky wrote: > Currently there is a check if the address being mapped is in the ISA > range (is_ISA_range()), and if it is then phys_to_virt() is used to > perform the mapping. When SME is active, however, this will result > in the mapping having the encryption bit

Re: [PATCH v7 06/36] x86/mm: Add Secure Memory Encryption (SME) support

On Fri, 16 Jun 2017, Tom Lendacky wrote: > > +config ARCH_HAS_MEM_ENCRYPT > + def_bool y > + depends on X86 That one is silly. The config switch is in the x86 KConfig file, so X86 is on. If you intended to move this to some generic place outside of x86/Kconfig then this should be

Re: [PATCH v7 19/36] x86/mm: Add support to access boot related data in the clear

On Fri, Jun 16, 2017 at 01:53:26PM -0500, Tom Lendacky wrote: > Boot data (such as EFI related data) is not encrypted when the system is > booted because UEFI/BIOS does not run with SME active. In order to access > this data properly it needs to be mapped decrypted. > > Update early_memremap() to

Re: [PATCH v8 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

On Tue, Jun 20, 2017 at 07:47:37PM +0530, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 implementation doesn't support second page in SMMU > register space. Hence, resource size is set as 64k for this model. > > Signed-off-by: Linu Cherian

Re: [PATCH v8 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option is enabled as an errata workaround. > This option when turned on, replaces

Re: [PATCH v8 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

On Tue, Jun 20, 2017 at 07:47:37PM +0530, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 implementation doesn't support second page in SMMU > register space. Hence, resource size is set as 64k for this model. > > Signed-off-by: Linu Cherian

Re: [PATCH v8 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote: > From: Geetha Sowjanya > > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq > lines for gerror, eventq and cmdq-sync. > > SHARED_IRQ option is set as a errata workaround,

Re: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

On Tue, Jun 20, 2017 at 03:39:30PM +, Shameerali Kolothum Thodi wrote: > > > > -Original Message- > > From: Robin Murphy [mailto:robin.mur...@arm.com] > > Sent: Tuesday, June 20, 2017 4:16 PM > > To: Shameerali Kolothum Thodi; Lorenzo Pieralisi > > Cc: marc.zyng...@arm.com;

Re: [PATCH v7 11/36] x86/mm: Add SME support for read_cr3_pa()

On 6/20/2017 11:17 AM, Andy Lutomirski wrote: On Fri, Jun 16, 2017 at 11:51 AM, Tom Lendacky wrote: The cr3 register entry can contain the SME encryption mask that indicates the PGD is encrypted. The encryption mask should not be used when creating a virtual address

Re: [PATCH v7 11/36] x86/mm: Add SME support for read_cr3_pa()

On Fri, Jun 16, 2017 at 11:51 AM, Tom Lendacky wrote: > The cr3 register entry can contain the SME encryption mask that indicates > the PGD is encrypted. The encryption mask should not be used when > creating a virtual address from the cr3 register, so remove the SME >

Re: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

On 20/06/17 16:51, Lorenzo Pieralisi wrote: > On Tue, Jun 20, 2017 at 04:16:18PM +0100, Robin Murphy wrote: >> On 20/06/17 15:07, Shameerali Kolothum Thodi wrote: >>> >>> -Original Message- From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] Sent: Tuesday, June 20,

Re: [PATCH v7 08/36] x86/mm: Add support to enable SME in early boot processing

On 6/20/2017 2:38 AM, Borislav Petkov wrote: On Fri, Jun 16, 2017 at 01:51:15PM -0500, Tom Lendacky wrote: Add support to the early boot code to use Secure Memory Encryption (SME). Since the kernel has been loaded into memory in a decrypted state, encrypt the kernel in place and update the

Re: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

On Tue, Jun 20, 2017 at 04:16:18PM +0100, Robin Murphy wrote: > On 20/06/17 15:07, Shameerali Kolothum Thodi wrote: > > > > > >> -Original Message- > >> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > >> Sent: Tuesday, June 20, 2017 11:29 AM > >> To: Shameerali Kolothum

RE: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

> -Original Message- > From: Robin Murphy [mailto:robin.mur...@arm.com] > Sent: Tuesday, June 20, 2017 4:16 PM > To: Shameerali Kolothum Thodi; Lorenzo Pieralisi > Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com; > hanjun@linaro.org; Gabriele Paoloni; John Garry;

Re: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

On 20/06/17 15:07, Shameerali Kolothum Thodi wrote: > > >> -Original Message- >> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] >> Sent: Tuesday, June 20, 2017 11:29 AM >> To: Shameerali Kolothum Thodi >> Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com; >>

[PATCH v8 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following patchset does software workaround for these

[PATCH v8 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

From: Geetha Sowjanya Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq lines for gerror, eventq and cmdq-sync. SHARED_IRQ option is set as a errata workaround, which allows to share the irq line by register single irq handler for all

[PATCH v8 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

From: Linu Cherian Cavium ThunderX2 SMMU implementation doesn't support page 1 register space and PAGE0_REGS_ONLY option is enabled as an errata workaround. This option when turned on, replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS register access

[PATCH v8 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

From: Linu Cherian Cavium ThunderX2 implementation doesn't support second page in SMMU register space. Hence, resource size is set as 64k for this model. Signed-off-by: Linu Cherian Signed-off-by: Geetha Sowjanya

RE: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

> -Original Message- > From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com] > Sent: Tuesday, June 20, 2017 11:29 AM > To: Shameerali Kolothum Thodi > Cc: marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com; > robin.mur...@arm.com; hanjun@linaro.org; Gabriele

Re: [PATCH 0/8] io-pgtable lock removal

On 15/06/17 01:40, Ray Jui wrote: > Hi Robin, > > I have applied this patch series on top of v4.12-rc4, and ran various > Ethernet and NVMf target throughput tests on it. > > To give you some background of my setup: > > The system is a ARMv8 based system with 8 cores. It has various PCIe > root

Re: clean up and modularize arch dma_mapping interface

On Tue, Jun 20, 2017 at 11:19:02AM +0200, Daniel Vetter wrote: > Ack for the 2 drm patches, but I can also pick them up through drm-misc if > you prefer that (but then it'll be 4.14). Nah, I'll plan to set up a dma-mapping tree so that we'll have common place for dma-mapping work.

Re: new dma-mapping tree, was Re: clean up and modularize arch dma_mapping interface V2

On Tue, Jun 20, 2017 at 11:04:00PM +1000, Stephen Rothwell wrote: > git://git.linaro.org/people/mszyprowski/linux-dma-mapping.git#dma-mapping-next > > Contacts: Marek Szyprowski and Kyungmin Park (cc'd) > > I have called your tree dma-mapping-hch for now. The other tree has > not been updated

Re: new dma-mapping tree, was Re: clean up and modularize arch dma_mapping interface V2

On Tue, Jun 20, 2017 at 02:14:36PM +0100, Robin Murphy wrote: > Hi Christoph, > > On 20/06/17 13:41, Christoph Hellwig wrote: > > On Fri, Jun 16, 2017 at 08:10:15PM +0200, Christoph Hellwig wrote: > >> I plan to create a new dma-mapping tree to collect all this work. > >> Any volunteers for

Re: new dma-mapping tree, was Re: clean up and modularize arch dma_mapping interface V2

Hi Christoph, On 20/06/17 13:41, Christoph Hellwig wrote: > On Fri, Jun 16, 2017 at 08:10:15PM +0200, Christoph Hellwig wrote: >> I plan to create a new dma-mapping tree to collect all this work. >> Any volunteers for co-maintainers, especially from the iommu gang? > > Ok, I've created the new

RE: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

> -Original Message- > From: Robin Murphy [mailto:robin.mur...@arm.com] > Sent: Monday, June 19, 2017 6:42 PM > To: Shameerali Kolothum Thodi; lorenzo.pieral...@arm.com; > marc.zyng...@arm.com; sudeep.ho...@arm.com; will.dea...@arm.com; > hanjun@linaro.org > Cc: Gabriele Paoloni;

Re: new dma-mapping tree, was Re: clean up and modularize arch dma_mapping interface V2

Hi Christoph, On Tue, 20 Jun 2017 14:41:40 +0200 Christoph Hellwig wrote: > > On Fri, Jun 16, 2017 at 08:10:15PM +0200, Christoph Hellwig wrote: > > I plan to create a new dma-mapping tree to collect all this work. > > Any volunteers for co-maintainers, especially from the iommu

new dma-mapping tree, was Re: clean up and modularize arch dma_mapping interface V2

On Fri, Jun 16, 2017 at 08:10:15PM +0200, Christoph Hellwig wrote: > I plan to create a new dma-mapping tree to collect all this work. > Any volunteers for co-maintainers, especially from the iommu gang? Ok, I've created the new tree: git://git.infradead.org/users/hch/dma-mapping.git for-next

Re: [PATCH 2/7] dt-bindings: PCI: Describe ATS property for root complex nodes

On 06/06/2017 12:11 PM, Jean-Philippe Brucker wrote: > On 05/06/17 18:20, Rob Herring wrote: >> pci-host-{e,}cam-generic is a special case. I'm okay with having a >> property for that I suppose. We should not require this property though >> and allow for it to be implied by the SoC specific

Re: [PATCH 1/1] iommu/arm-smmu-v3: replace writel with writel_relaxed in queue_inc_prod

On 20/06/17 12:04, Zhen Lei wrote: > This function is protected by spinlock, and the latter will do memory > barrier implicitly. So that we can safely use writel_relaxed. In fact, the > dmb operation will lengthen the time protected by lock, which indirectly > increase the locking confliction in

[PATCH 1/1] iommu/arm-smmu-v3: replace writel with writel_relaxed in queue_inc_prod

This function is protected by spinlock, and the latter will do memory barrier implicitly. So that we can safely use writel_relaxed. In fact, the dmb operation will lengthen the time protected by lock, which indirectly increase the locking confliction in the stress scene. Signed-off-by: Zhen Lei

Re: [PATCH v2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801

Hi Shameer, On Mon, Jun 19, 2017 at 04:45:00PM +0100, shameer wrote: > The HiSilicon erratum 161010801 describes the limitation of HiSilicon > platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. > > On these platforms GICv3 ITS translator is presented with the deviceID > by

Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

On 20.06.17 10:19:43, Robert Richter wrote: > On 30.05.17 17:33:39, Geetha sowjanya wrote: > > From: Linu Cherian > > + /* > > +* Override the size, for Cavium ThunderX2 implementation > > +* which doesn't support the page 1 SMMU register space. > > +*/ > >

Re: [PATCH v7 11/36] x86/mm: Add SME support for read_cr3_pa()

On Fri, Jun 16, 2017 at 01:51:55PM -0500, Tom Lendacky wrote: > The cr3 register entry can contain the SME encryption mask that indicates > the PGD is encrypted. The encryption mask should not be used when > creating a virtual address from the cr3 register, so remove the SME > encryption mask in

Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

On 30.05.17 17:33:39, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 implementation doesn't support second page in SMMU > register space. Hence, resource size is set as 64k for this model. > > Signed-off-by: Linu Cherian >

Re: [PATCH v7 08/36] x86/mm: Add support to enable SME in early boot processing

On Fri, Jun 16, 2017 at 01:51:15PM -0500, Tom Lendacky wrote: > Add support to the early boot code to use Secure Memory Encryption (SME). > Since the kernel has been loaded into memory in a decrypted state, encrypt > the kernel in place and update the early pagetables with the memory > encryption

Re: [PATCH v7 03/36] x86, mpparse, x86/acpi, x86/PCI, x86/dmi, SFI: Use memremap for RAM mappings

On Fri, Jun 16, 2017 at 01:50:23PM -0500, Tom Lendacky wrote: > The ioremap() function is intended for mapping MMIO. For RAM, the > memremap() function should be used. Convert calls from ioremap() to > memremap() when re-mapping RAM. > > This will be used later by SME to control how the