On Wed, Nov 13, 2019 at 12:11:32PM -0800, David Miller wrote:
> > This series introduces a few new dma unmap and sync api variants that,
> > on top of what the originals do, return the virtual address
> > corresponding to the input dma address. In order to do that a new dma
> > map op is added, .ge
Robin, does this mean you ACK this series for the powerpc use case?
Alexey and other ppc folks: can you take a look?
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On Tue, Nov 19, 2019 at 05:17:03PM +, Robin Murphy wrote:
> TBH I can't see it being a massive problem even if the DMA patch, driver
> and DTS patch went entirely separately via the respective DMA, PCI, and
> arm-soc trees in the same cycle. Bisecting over a merge window is a big
> enough pa
On Sat, Nov 16, 2019 at 08:06:05AM +0100, Christian Zigotzky wrote:
> /*
> * DMA addressing mode.
> *
> * 0 : 32 bit addressing for all chips.
> * 1 : 40 bit addressing when supported by chip.
> * 2 : 64 bit addressing when supported by chip,
> * limited to 16 segments of 4 GB -> 64
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^/\t/' -i */Kconfig
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Fix also 7-space and tab+1 space indentation issues.
---
drivers/iommu/Kconfig | 6 +++-
Both find_iova() and __free_iova() take iova_rbtree_lock,
there is no reason to take and release it twice inside
free_iova().
Fold them into the critical section by calling the unlock
versions instead.
Cc: Joerg Roedel
Signed-off-by: Cong Wang
---
drivers/iommu/iova.c | 8 ++--
1 file chan
This patchset contains three small optimizations for the global spinlock
contention in IOVA cache. Our memcache perf test shows this reduced its
p999 latency down by 45% on AMD when IOMMU is enabled.
Cong Wang (3):
iommu: match the original algorithm
iommu: optimize iova_magazine_free_pfns()
If the maganize is empty, iova_magazine_free_pfns() should
be a nop, however it misses the case of mag->size==0. So we
should just call iova_magazine_empty().
This should reduce the contention on iovad->iova_rbtree_lock
a little bit.
Cc: Joerg Roedel
Signed-off-by: Cong Wang
---
drivers/iommu/
The IOVA cache algorithm implemented in IOMMU code does not
exactly match the original algorithm described in the paper.
Particularly, it doesn't need to free the loaded empty magazine
when trying to put it back to global depot.
This patch makes it exactly match the original algorithm.
Cc: Joerg
On Wed, 20 Nov 2019 22:06:24 +0100
Auger Eric wrote:
> Hi Jacob,
>
> On 11/19/19 6:56 PM, Jacob Pan wrote:
> > Make use of generic IOASID code to manage PASID allocation,
> > free, and lookup. Replace Intel specific code.
> > IOASID allocator is inclusive for both start and end of the
> > alloca
On Wed, Nov 20, 2019 at 11:00 AM Will Deacon wrote:
>
> Commit 8e12257dead7 ("of: property: Add device link support for iommus,
> mboxes and io-channels") added device link support for IOMMU linkages
> described using the "iommus" property. For PCI devices, this property
> is not present and inste
Hi Jacob,
On 11/19/19 6:56 PM, Jacob Pan wrote:
> When setting up first level page tables for sharing with CPU, we need
> to ensure IOMMU can support no less than the levels supported by the
> CPU.
>
> It is not adequate, as in the current code, to set up 5-level paging
> in PASID entry First Leve
Hi Jacob,
On 11/19/19 6:56 PM, Jacob Pan wrote:
> Page responses should only be sent when last page in group (LPIG) or
> private data is present in the page request. This patch avoids sending
> invalid descriptors.
>
> Fixes: 5d308fc1ecf53 ("iommu/vt-d: Add 256-bit invalidation descriptor
> suppo
Hi Jacob,
On 11/19/19 6:56 PM, Jacob Pan wrote:
> Make use of generic IOASID code to manage PASID allocation,
> free, and lookup. Replace Intel specific code.
> IOASID allocator is inclusive for both start and end of the allocation
> range. The current code is based on IDR, which is exclusive for
Hi Jacob,
On 11/19/19 6:56 PM, Jacob Pan wrote:
> After each setup for PASID entry, related translation caches must be
> flushed. We can combine duplicated code into one function which is less
> error prone.
>
> Signed-off-by: Jacob Pan
> Reviewed-by: Lu Baolu
> Acked-by: Lu Baolu
I sent my R-
Hi
On 11/19/19 6:56 PM, Jacob Pan wrote:
> PASID allocator uses IDR which is exclusive for the end of the
> allocation range. There is no need to decrement pasid_max.
>
> Fixes: af39507305fb ("iommu/vt-d: Apply global PASID in SVA")
> Reported-by: Eric Auger
> Signed-off-by: Jacob Pan
> Acked-b
Hi Jacob,
On 11/19/19 6:56 PM, Jacob Pan wrote:
> Shared Virtual Memory(SVM) is based on a collective set of hardware
> features detected at runtime. There are requirements for matching CPU
> and IOMMU capabilities.
>
> The current code checks CPU and IOMMU feature set for SVM support but
> the r
Hi Jacob,
On 11/19/19 6:56 PM, Jacob Pan wrote:
> Add a check during SVM bind to ensure CPU and IOMMU hardware capabilities
> are met.
>
> Signed-off-by: Jacob Pan
> Acked-by: Lu Baolu
I sent my Rb on v2:
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> drivers/iommu/intel-svm.c | 3 +++
> 1 fil
On 2019-11-20 10:48 a.m., Dmitry Safonov wrote:
> +Cc: linux-...@vger.kernel.org
> +Cc: Bjorn Helgaas
> +Cc: Logan Gunthorpe
>
> On 11/5/19 12:17 PM, James Sewart wrote:
>> Any comments on this?
>>
>> Cheers,
>> James.
>>
>>> On 24 Oct 2019, at 13:52, James Sewart wrote:
>>>
>>> The PLX PEX
On Wed, Nov 20, 2019 at 12:30:48PM -0700, Logan Gunthorpe wrote:
> On 2019-11-20 10:48 a.m., Dmitry Safonov wrote:
> > On 11/5/19 12:17 PM, James Sewart wrote:
> >>
> >>> On 24 Oct 2019, at 13:52, James Sewart wrote:
> >>>
> >>> The PLX PEX NTB forwards DMA transactions using Requester ID's that d
this helps! *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
next/master bisection: boot on peach-pi
Summary:
Start: 1fef9976397f Add linux-next specific files for 20191120
Details:https://kernelci.org/boot/id/5dd5175059b514
[+cc Alex]
Hi James,
Thanks for the patch, and thanks, Dmitry for the cc!
"scripts/get_maintainer.pl -f drivers/pci/quirks.c" will give you a
list of relevant email addresses to post patches. It was a good idea
to augment that list with related addresses, e.g., Logan and the iommu
list.
Follow
On Mon, Nov 04, 2019 at 04:40:06PM -0700, Jordan Crouse wrote:
> On Fri, Oct 25, 2019 at 07:08:39PM +0100, Robin Murphy wrote:
> > Now that we can correctly extract top-level indices without relying on
> > the remaining upper bits being zero, the only remaining impediments to
> > using a given tabl
Commit 8e12257dead7 ("of: property: Add device link support for iommus,
mboxes and io-channels") added device link support for IOMMU linkages
described using the "iommus" property. For PCI devices, this property
is not present and instead the "iommu-map" property is used on the host
bridge node to
+Cc: linux-...@vger.kernel.org
+Cc: Bjorn Helgaas
+Cc: Logan Gunthorpe
On 11/5/19 12:17 PM, James Sewart wrote:
> Any comments on this?
>
> Cheers,
> James.
>
>> On 24 Oct 2019, at 13:52, James Sewart wrote:
>>
>> The PLX PEX NTB forwards DMA transactions using Requester ID's that don't
>> e
On Wed, Nov 13, 2019 at 04:11:38PM +, Shameer Kolothum wrote:
> CMDQ_OP_TLBI_NH_VA requires VMID and this was missing since
> commit 1c27df1c0a82 ("iommu/arm-smmu: Use correct address mask
> for CMD_TLBI_S2_IPA"). Add it back.
>
> Fixes: 1c27df1c0a82 ("iommu/arm-smmu: Use correct address mask
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