On Fri, Oct 30, 2020 at 7:12 AM Robin Murphy wrote:
> On 2020-10-30 01:02, John Stultz wrote:
> > On Wed, Oct 28, 2020 at 7:51 AM Robin Murphy wrote:
> >> Hmm, perhaps I'm missing something here, but even if the config options
> >> *do* line up, what prevents arm-smmu probing before qcom-scm and
Allow the qcom_scm driver to be loadable as a permenent module.
This still uses the "depends on QCOM_SCM || !QCOM_SCM" bit to
ensure that drivers that call into the qcom_scm driver are
also built as modules. While not ideal in some cases its the
only safe way I can find to avoid build errors
Tweaks to allow pinctrl-msm code to be loadable as a module.
This is needed in order to support having the qcom-scm driver,
which pinctrl-msm calls into, configured as a module.
This requires that we tweak Kconfigs selecting PINCTRL_MSM to
also depend on QCOM_SCM || QCOM_SCM=n so that we match
In trying to handle a possible driver probe ordering issue
brought up by Robin Murphy, I ran across a separate null pointer
crash in the iommu core in iommu_group_remove_device():
[2.732803] dwc3-qcom a6f8800.usb: failed to get usb-ddr path: -517
[2.739281] Unable to handle kernel NULL
Robin Murphy pointed out that if the arm-smmu driver probes before
the qcom_scm driver, we may call qcom_scm_qsmmu500_wait_safe_toggle()
before the __scm is initialized.
Now, getting this to happen is a bit contrived, as in my efforts it
required enabling asynchronous probing for both drivers,
On Fri, 30 Oct 2020 06:16:28 +
"Tian, Kevin" wrote:
> > From: Lu Baolu
> > Sent: Friday, October 30, 2020 12:58 PM
> >
> > With the IOMMU driver registering iommu_ops for the mdev_bus, the
> > IOMMU
> > operations on an mdev could be done in the same way as any normal device
> > (for
On Fri, 30 Oct 2020 12:58:08 +0800
Lu Baolu wrote:
> +static const struct iommu_ops siov_iommu_ops = {
> + .capable= intel_iommu_capable,
> + .domain_alloc = siov_iommu_domain_alloc,
> + .domain_free= intel_iommu_domain_free,
> + .attach_dev
There is no reason to use GFP_ATOMIC in a 'suspend' function.
Use GFP_KERNEL instead to give more opportunities to allocate the
requested memory.
Signed-off-by: Christophe JAILLET
---
Should GFP_ATOMIC be mandatory here, a comment explaining why would be great
---
drivers/iommu/intel/iommu.c |
On 29/10/20 23:12, David Laight wrote:
>> https://godbolt.org/z/4dzPbM
>>
>> With -fno-strict-aliasing, the compiler reloads the pointer if you write
>> to the start of what it points to, but not if you write to later
>> elements.
> I guess it assumes that global data doesn't overlap.
Yeah,
On Thu, Oct 29, 2020 at 06:25:43PM +0100, Nicolas Saenz Julienne wrote:
> Ard Biesheuvel (1):
> arm64: mm: Set ZONE_DMA size based on early IORT scan
>
> Nicolas Saenz Julienne (6):
> arm64: mm: Move reserve_crashkernel() into mem_init()
> arm64: mm: Move zone_dma_bits initialization into
On Thu, Oct 29, 2020 at 06:25:49PM +0100, Nicolas Saenz Julienne wrote:
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index 9929ff50c0c0..05fe4a076bab 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -1718,3 +1718,55 @@ void __init
On Fri, 30 Oct 2020 12:58:05 +0800
Lu Baolu wrote:
> Move mdev bus registration earlier than IOMMU probe processing so that
> the IOMMU drivers could be able to set iommu_ops for the mdev bus. This
> only applies when vfio-mdev module is setected to be built-in.
>
> Signed-off-by: Lu Baolu
>
On 2020-10-29 21:39, Song Bao Hua (Barry Song) wrote:
[...]
+struct map_benchmark {
+ __u64 map_nsec;
+ __u64 unmap_nsec;
+ __u32 threads; /* how many threads will do map/unmap in parallel */
+ __u32 seconds; /* how long the test will last */
+ int node; /* which
On 2020-10-30 01:02, John Stultz wrote:
On Wed, Oct 28, 2020 at 7:51 AM Robin Murphy wrote:
Hmm, perhaps I'm missing something here, but even if the config options
*do* line up, what prevents arm-smmu probing before qcom-scm and
dereferencing NULL in qcom_scm_qsmmu500_wait_safe_toggle() before
From: Arnd Bergmann
There are hundreds of warnings in a W=2 build about a local
variable shadowing the global 'apic' definition:
arch/x86/kvm/lapic.h:149:65: warning: declaration of 'apic' shadows a global
declaration [-Wshadow]
Avoid this by renaming the global 'apic' variable to the more
On Fri, 30 Oct 2020 17:12:52 +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
>
> CC: Fabien Parent
> CC: Ming-Fan Chen
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
> ---
> .../mediatek,smi-common.txt | 50 ---
> .../mediatek,smi-common.yaml
On 10/30/20 10:37 AM, Yi Sun wrote:
From: "Liu, Yi L"
In prq_event_thread(), the QI_PGRP_PDP is wrongly set by
'req->pasid_present' which should be replaced to
'req->priv_data_present'.
Fixes: 5b438f4ba315 ("iommu/vt-d: Support page request in scalable mode")
Signed-off-by: Liu, Yi L
On 10/30/20 10:37 AM, Yi Sun wrote:
From: Liu Yi L
Should get correct sid and set it into sdev. Because we execute
'sdev->sid != req->rid' in the loop of prq_event_thread().
Fixes: eb8d93ea3c1d ("iommu/vt-d: Report page request faults for guest SVA")
Signed-off-by: Liu Yi L
Signed-off-by: Yi
On Fri, Oct 30, 2020 at 05:55:53AM +, Tian, Kevin wrote:
> > From: Lu Baolu
> > Sent: Friday, October 30, 2020 12:58 PM
> >
> > The aux-domain apis were designed for macro driver where the subdevices
> > are created and used inside a device driver. Use the device's bus iommu
> > ops instead
On Mon, Oct 26, 2020 at 02:05:06PM -0700, Jacob Pan wrote:
> > This looks good to me, with small comments below.
> >
> Can I add your Reviewed-by tag after addressing the comments?
Yes sure, this took forever to review so I'm happy not to do another pass :)
> > > +Each IOASID set is created
On Fri, 2020-10-02 at 12:58 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > Convert MediaTek IOMMU to DT schema.
> >
> > Signed-off-by: Yong Wu
> > ---
> > .../bindings/iommu/mediatek,iommu.txt | 103
> >
Hi Robin,
On 29.10.2020 16:34, Robin Murphy wrote:
> A common idiom for .of_xlate is to use of_find_device_by_node() to
> retrieve the relevant IOMMU instance data when translating IOMMU
> specifiers for a client device. Although it's slightly roundabout,
> this is simply looking up something we
> From: h...@lst.de
> Sent: Wednesday, October 28, 2020 11:01 PM
>
> On Tue, Oct 27, 2020 at 12:52:30PM +, Parav Pandit wrote:
> >
> > > From: h...@lst.de
> > > Sent: Tuesday, October 27, 2020 1:41 PM
> > >
> > > On Mon, Oct 26, 2020 at 05:23:48AM +, Parav Pandit wrote:
> > > > Hi
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well the SMMU pagetables.
This helps with improved render
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffers and the other slice is used for
caching the GPU SMMU pagetables. This talks to the core system
cache driver to acquire
From: Jordan Crouse
This is an extension to the series [1] to enable the System Cache (LLC) for
Adreno a6xx targets.
GPU targets with an MMU-500 attached have a slightly different process for
enabling system cache. Use the compatible string on the IOMMU phandle
to see if an MMU-500 is attached
From: Sharat Masetty
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
Signed-off-by: Sai
Convert MediaTek SMI to DT schema.
CC: Fabien Parent
CC: Ming-Fan Chen
CC: Matthias Brugger
Signed-off-by: Yong Wu
---
.../mediatek,smi-common.txt | 50 ---
.../mediatek,smi-common.yaml | 140 ++
Add mt8192 smi support.
Signed-off-by: Yong Wu
---
drivers/memory/mtk-smi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 691e4c344cf8..ac350f8d1e20 100644
--- a/drivers/memory/mtk-smi.c
+++
This patchset mainly adds SMI support for mt8192.
It comes from the patchset[1]. I seperate the smi part into this patchset.
And the two part(IOMMU/SMI) patchset don't depend on each other.
Rebase on v5.10-rc1.
changenote:
v4: add if-then segment in the binding.
v3: [1].
[1]
Add mt8192 smi support in the bindings.
Signed-off-by: Yong Wu
Reviewed-by: Rob Herring
---
.../bindings/memory-controllers/mediatek,smi-common.yaml | 4 +++-
.../bindings/memory-controllers/mediatek,smi-larb.yaml| 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
On 22/09/2020 16:16, Robin Murphy wrote:
> Hi all,
>
> Here's a quick v2 with the tags so far picked up and some inline
> commentary about the shareability domains for the pagetable code.
>
> Robin.
>
>
> Robin Murphy (3):
> iommu/io-pgtable-arm: Support coherency for Mali LPAE
>
> diff --git a/drivers/net/wireless/ath/ath10k/Kconfig
> b/drivers/net/wireless/ath/ath10k/Kconfig
> index 40f91bc8514d8..a490e78890017 100644
> --- a/drivers/net/wireless/ath/ath10k/Kconfig
> +++ b/drivers/net/wireless/ath/ath10k/Kconfig
> @@ -44,6 +44,7 @@ config ATH10K_SNOC
> tristate
> From: Lu Baolu
> Sent: Friday, October 30, 2020 12:58 PM
>
> With the IOMMU driver registering iommu_ops for the mdev_bus, the
> IOMMU
> operations on an mdev could be done in the same way as any normal device
> (for example, PCI/PCIe). There's no need to distinguish an mdev from
> others for
> From: Lu Baolu
> Sent: Friday, October 30, 2020 12:58 PM
>
> The iommu_ops will only take effect when INTEL_IOMMU_SCALABLE_IOV
> kernel
> option is selected. It applies to any device passthrough framework which
> implements an underlying bus for the subdevices.
>
> - Subdevice probe:
> When
Tweaks to allow pinctrl-msm code to be loadable as a module.
This is needed in order to support having the qcom-scm driver,
which pinctrl-msm calls into, configured as a module.
This requires that we tweak Kconfigs selecting PINCTRL_MSM to
also depend on QCOM_SCM || QCOM_SCM=n so that we match
Allow the qcom_scm driver to be loadable as a permenent module.
This still uses the "depends on QCOM_SCM || !QCOM_SCM" bit to
ensure that drivers that call into the qcom_scm driver are
also built as modules. While not ideal in some cases its the
only safe way I can find to avoid build errors
On Wed, Oct 28, 2020 at 6:51 AM Will Deacon wrote:
> On Tue, Oct 27, 2020 at 10:53:47PM -0700, John Stultz wrote:
> > Alternatively, I'm considering trying to switch the module dependency
> > annotation so that the CONFIG_QCOM_SCM modularity depends on ARM_SMMU
> > being a module. But that is
42 matches
Mail list logo
