[PATCH v2] iommu/arm-smmu: fix some checkpatch issues

)) | since it seems to be a case where exceeding 80 columns significantly increases readability and does not hide information. (Documentation/CodingStyle). Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Changelog: - v2: submitted against will/iommu/staging, added to commit message

[PATCH] iommu/arm-smmu: avoid calling request_irq in atomic context

interrupt handler so we shouldn't be missing any interrupts. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- drivers/iommu/arm-smmu.c | 37 + 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu

[PATCH v2] iommu/arm-smmu: avoid calling request_irq in atomic context

interrupt handler so we shouldn't be missing any interrupts. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Changelog: - v2: return error code from request_irq on failure --- drivers/iommu/arm-smmu.c | 37 + 1 file changed, 17 insertions(+), 20

Re: [PATCH v2] iommu/arm-smmu: avoid calling request_irq in atomic context

On Mon, Jul 28 2014 at 12:03:27 PM, Will Deacon will.dea...@arm.com wrote: Hi Mitchel, Thanks for the quick v2, but now I spotted a problem :) On Mon, Jul 28, 2014 at 07:38:12PM +0100, Mitchel Humpherys wrote: static void arm_smmu_destroy_domain_context(struct iommu_domain *domain

[PATCH v3] iommu/arm-smmu: avoid calling request_irq in atomic context

interrupt handler so we shouldn't be missing any interrupts. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Changelog: - v3: rework irq request code to avoid requesting the irq every time a master is added to the domain - v2: return error code from request_irq on failure

Re: [PATCH v3] iommu/arm-smmu: avoid calling request_irq in atomic context

On Wed, Jul 30 2014 at 08:31:14 AM, Will Deacon will.dea...@arm.com wrote: Hey Mitch, On Tue, Jul 29, 2014 at 07:11:15PM +0100, Mitchel Humpherys wrote: request_irq shouldn't be called from atomic context since it might sleep, but we're calling it with a spinlock held, resulting

[PATCH v4] iommu/arm-smmu: avoid calling request_irq in atomic context

interrupt handler so we shouldn't be missing any interrupts. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Changelog: - v4: some cleanup suggested by Will - v3: rework irq request code to avoid requesting the irq every time a master is added to the domain - v2: return

[PATCH 0/6] iommu/arm-smmu: misc features, new DT bindings

and sixth handle some implementation-specific issues, providing knobs in the device tree and a new domain attribute. This series is based on on Will's iommu/pci branch. Mitchel Humpherys (6): iommu/arm-smmu: add support for specifying clocks iommu/arm-smmu: add support for specifying

[PATCH 5/6] iommu/arm-smmu: support buggy implementations with invalidate-on-map

Add a workaround for some buggy hardware that requires a TLB invalidate operation to occur at map time. Activate the feature with the qcom,smmu-invalidate-on-map boolean DT property. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Documentation/devicetree/bindings/iommu/arm,smmu.txt

[PATCH 4/6] iommu/arm-smmu: implement generic DT bindings

Generic IOMMU device tree bindings were recently added in [devicetree: Add generic IOMMU device tree bindings]. Implement the bindings in the ARM SMMU driver. See Documentation/devicetree/bindings/iommu/iommu.txt for the bindings themselves. Signed-off-by: Mitchel Humpherys mitch

[PATCH 1/6] iommu/arm-smmu: add support for specifying clocks

for SMMU register access and turn them on and off as needed. If no clocks are specified in the device tree things continue to work the way they always have: we assume all necessary clocks are always turned on. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- .../devicetree/bindings

[PATCH 2/6] iommu/arm-smmu: add support for specifying regulators

On some power-constrained platforms it's useful to disable power when a device is not in use. Add support for specifying regulators for SMMUs and only leave power on as long as the SMMU is in use (attached). Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- .../devicetree/bindings

[PATCH 3/6] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

[PATCH 6/6] iommu/arm-smmu: add .domain_{set, get}_attr for coherent walk control

Under certain conditions coherent hardware translation table walks can result in degraded performance. Add a new domain attribute to disable/enable this feature in generic code along with the domain attribute setter and getter to handle it in the ARM SMMU driver. Signed-off-by: Mitchel Humpherys

Re: [PATCH 4/6] iommu/arm-smmu: implement generic DT bindings

On Tue, Aug 12 2014 at 05:51:37 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: Generic IOMMU device tree bindings were recently added in [devicetree: Add generic IOMMU device tree bindings]. Implement the bindings in the ARM SMMU driver. See Documentation/devicetree/bindings/iommu

Re: [PATCH 0/6] iommu/arm-smmu: misc features, new DT bindings

On Tue, Aug 12 2014 at 05:51:33 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: This series is based on on Will's iommu/pci branch. Incredibly, I also neglected to base this on top of Olav's recent patch (iommu/arm-smmu: Do not access non-existing SMR registers)! I will do that in v2 after

Re: [PATCH 1/6] iommu/arm-smmu: add support for specifying clocks

Well hopefully this isn't too Nick Krouse-esque, but I have some comments on my own patch below. I sat on these for a few days but have noticed a few things after testing on another platform... On Tue, Aug 12 2014 at 05:51:34 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: On some

Re: [PATCH 2/6] iommu/arm-smmu: add support for specifying regulators

On Tue, Aug 12 2014 at 05:51:35 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: On some power-constrained platforms it's useful to disable power when a device is not in use. Add support for specifying regulators for SMMUs and only leave power on as long as the SMMU is in use (attached

Re: [PATCH 3/6] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

On Tue, Aug 19 2014 at 05:44:32 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Aug 13, 2014 at 01:51:36AM +0100, Mitchel Humpherys wrote: Currently, we provide the iommu_ops.iova_to_phys service by doing a table walk in software to translate IO virtual addresses to physical addresses

Re: [PATCH 6/6] iommu/arm-smmu: add .domain_{set, get}_attr for coherent walk control

On Tue, Aug 19 2014 at 05:48:07 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Aug 13, 2014 at 01:51:39AM +0100, Mitchel Humpherys wrote: Under certain conditions coherent hardware translation table walks can result in degraded performance. Add a new domain attribute to disable/enable

Re: [PATCH 1/6] iommu/arm-smmu: add support for specifying clocks

On Tue, Aug 19 2014 at 05:58:34 AM, Will Deacon will.dea...@arm.com wrote: I also assume that the clk API ignores calls to clk_enable_prepare for a clk that's already enabled? I couldn't find that code... That's clk_prepare_enable, not clk_enable_prepare. It's in linux/clk.h. -Mitch -- The

Re: [PATCH 1/6] iommu/arm-smmu: add support for specifying clocks

On Wed, Sep 10 2014 at 11:27:39 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Sep 10, 2014 at 02:29:42AM +0100, Mitchel Humpherys wrote: On Tue, Aug 26 2014 at 07:27:58 AM, Will Deacon will.dea...@arm.com wrote: On Tue, Aug 19, 2014 at 08:03:09PM +0100, Olav Haugan wrote: Clients

[PATCH 1/2] iopoll: Introduce memory-mapped IO polling macros

thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- include/linux/iopoll.h | 114 + 1 file changed, 114 insertions(+) create mode

[PATCH 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

Re: [PATCH 0/2] iommu/arm-smmu: hard iova_to_phys

On Thu, Sep 11 2014 at 11:30:42 AM, Mitchel Humpherys mitch...@codeaurora.org wrote: This series introduces support for performing iova-to-phys translations via the ARM SMMU hardware on supported implementations. We also make use of some new generic macros for polling hardware registers

Re: [PATCH 1/6] iommu/arm-smmu: add support for specifying clocks

On Wed, Sep 10 2014 at 12:09:06 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: On Wed, Sep 10 2014 at 11:27:39 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Sep 10, 2014 at 02:29:42AM +0100, Mitchel Humpherys wrote: On Tue, Aug 26 2014 at 07:27:58 AM, Will Deacon will.dea...@arm.com

[PATCH 1/2] iommu: add IOMMU_PRIV flag for access-protected mappings

Some IOMMUs support access-protected mappings. Add a mapping flag to indicate that the mapping should be created with access protection configured. Cc: Shubhraprakash Das sa...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- include/linux/iommu.h | 1 + 1 file changed

[PATCH 0/2] Add access-protected IOMMU mappings

This series introduces a new mapping flag to indicate that the mapping should be created with access protection applied. Support for this new flag is then added to the ARM SMMU driver. Mitchel Humpherys (2): iommu: add IOMMU_PRIV flag for access-protected mappings iommu/arm-smmu: add support

[PATCH 2/2] iommu/arm-smmu: add support for access-protected mappings

with nearby code. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- drivers/iommu/arm-smmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index ca18d6d42a..93999ec22c 100644 --- a/drivers/iommu/arm-smmu.c +++ b

[PATCH] iommu/arm-smmu: fix bug in pmd construction

only ever seem to iterate this loop once. However, things might change in the future that might cause us to hit this. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Will, I was unable to come up with a test case to hit this bug based on what I said in the commit message above. Not sure

Re: [PATCH 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

On Mon, Sep 22 2014 at 08:26:14 AM, Will Deacon will.dea...@arm.com wrote: Hi Mitch, On Thu, Sep 11, 2014 at 07:30:44PM +0100, Mitchel Humpherys wrote: Currently, we provide the iommu_ops.iova_to_phys service by doing a table walk in software to translate IO virtual addresses to physical

Re: [PATCH 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

On Wed, Sep 24 2014 at 09:37:12 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Sep 24, 2014 at 02:12:00AM +0100, Mitchel Humpherys wrote: On Mon, Sep 22 2014 at 08:26:14 AM, Will Deacon will.dea...@arm.com wrote: On Thu, Sep 11, 2014 at 07:30:44PM +0100, Mitchel Humpherys wrote

Re: [PATCH 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

On Fri, Sep 26 2014 at 03:24:30 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Sep 24, 2014 at 09:34:26PM +0100, Mitchel Humpherys wrote: On Wed, Sep 24 2014 at 09:37:12 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Sep 24, 2014 at 02:12:00AM +0100, Mitchel Humpherys wrote: On Mon

[PATCH v2 0/2] iommu/arm-smmu: hard iova_to_phys

' suffix - Removed some convenience iopoll wrappers to encourage explicitness Matt Wagantall (1): iopoll: Introduce memory-mapped IO polling macros Mitchel Humpherys (1): iommu/arm-smmu: add support for iova_to_phys through ATS1PR drivers/iommu/arm-smmu.c | 73

[PATCH v2 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

Re: [PATCH v2 0/2] iommu/arm-smmu: hard iova_to_phys

On Sat, Sep 27 2014 at 02:31:51 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: This series introduces support for performing iova-to-phys translations via the ARM SMMU hardware on supported implementations. We also make use of some new generic macros for polling hardware registers

[PATCH v3 1/2] iopoll: Introduce memory-mapped IO polling macros

thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- include/linux/iopoll.h | 77 ++ 1 file changed, 77 insertions(+) create mode 100644

[PATCH v3 0/2] iommu/arm-smmu: hard iova_to_phys

- Removed some convenience iopoll wrappers to encourage explicitness v2..v3: - Remomved unnecessary `dev_name's Matt Wagantall (1): iopoll: Introduce memory-mapped IO polling macros Mitchel Humpherys (1): iommu/arm-smmu: add support for iova_to_phys through ATS1PR drivers/iommu/arm

[PATCH v3 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

Re: [PATCH v3 1/2] iopoll: Introduce memory-mapped IO polling macros

On Mon, Sep 29 2014 at 01:31:37 AM, Thierry Reding thierry.red...@gmail.com wrote: On Sat, Sep 27, 2014 at 08:27:28PM -0700, Mitchel Humpherys wrote: From: Matt Wagantall ma...@codeaurora.org It is sometimes necessary to poll a memory-mapped register until its value satisfies some condition

[PATCH v4 0/2] iommu/arm-smmu: hard iova_to_phys

): iopoll: Introduce memory-mapped IO polling macros Mitchel Humpherys (1): iommu/arm-smmu: add support for iova_to_phys through ATS1PR drivers/iommu/arm-smmu.c | 79 +++- include/linux/iopoll.h | 77 ++ 2

[PATCH v4 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

[PATCH v4 1/2] iopoll: Introduce memory-mapped IO polling macros

Reding thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Changes since v3: - Updated commit message to better reflect the patch content --- include/linux/iopoll.h | 77

Re: [PATCH v3 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

On Tue, Sep 30 2014 at 03:23:34 AM, Will Deacon will.dea...@arm.com wrote: Hi Mitch, On Sun, Sep 28, 2014 at 04:27:29AM +0100, Mitchel Humpherys wrote: Currently, we provide the iommu_ops.iova_to_phys service by doing a table walk in software to translate IO virtual addresses to physical

Re: [PATCH v4 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

On Wed, Oct 01 2014 at 01:27:27 AM, Arnd Bergmann a...@arndb.de wrote: On Tuesday 30 September 2014 18:28:13 Mitchel Humpherys wrote: + if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp, + !(tmp ATSR_ACTIVE), 50, 100)) { This looks really bad

Re: [RFC][PATCH 2/2] Add support of the IOMMU_DEVICE flag.

On Mon, Oct 06 2014 at 03:28:16 AM, Varun Sethi varun.se...@freescale.com wrote: This flag is used for specifying access to device memory. SMMU would apply device memory attributes for a DMA transaction. This is required for setting access to GIC registers, for generating message interrupts.

Re: [PATCH v4 1/2] iopoll: Introduce memory-mapped IO polling macros

On Wed, Oct 01 2014 at 01:25:33 AM, Arnd Bergmann a...@arndb.de wrote: On Tuesday 30 September 2014 18:28:12 Mitchel Humpherys wrote: + */ +#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \ +({ \ + ktime_t timeout = ktime_add_us(ktime_get(), timeout_us

Re: [PATCH v4 1/2] iopoll: Introduce memory-mapped IO polling macros

On Tue, Oct 07 2014 at 06:47:59 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: +#define readl_poll_timeout_atomic(addr, val, cond, max_reads, time_between_us) \ +({ \ + int count; \ + for (count = (max_reads); count 0; count--) { \ + (val) = readl(addr

[PATCH v5 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

[PATCH v5 1/2] iopoll: Introduce memory-mapped IO polling macros

Reding thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Changes since v4: - Added support for other accessor functions - Unified atomic and non-atomic interfaces - Fixed

Re: [PATCH v4 1/2] iopoll: Introduce memory-mapped IO polling macros

On Wed, Oct 08 2014 at 06:40:46 AM, Arnd Bergmann a...@arndb.de wrote: On Tuesday 07 October 2014 18:47:59 Mitchel Humpherys wrote: On Wed, Oct 01 2014 at 01:25:33 AM, Arnd Bergmann a...@arndb.de wrote: On Tuesday 30 September 2014 18:28:12 Mitchel Humpherys wrote: + */ +#define

[PATCH v6 0/2] iommu/arm-smmu: hard iova_to_phys

to encourage explicitness Matt Wagantall (1): iopoll: Introduce memory-mapped IO polling macros Mitchel Humpherys (1): iommu/arm-smmu: add support for iova_to_phys through ATS1PR drivers/iommu/arm-smmu.c | 79 +- include/linux/iopoll.h | 213

[PATCH v6 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

Re: [PATCH v6 1/2] iopoll: Introduce memory-mapped IO polling macros

On Tue, Oct 14 2014 at 02:53:29 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: From: Matt Wagantall ma...@codeaurora.org It is sometimes necessary to poll a memory-mapped register until its value satisfies some condition. Introduce a family of convenience macros that do this. Tight

[PATCH v7 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys mitch

[PATCH v7 1/2] iopoll: Introduce memory-mapped IO polling macros

Reding thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Changes since v6: - No changes. Resending due to changes in the the next patch in the series. --- include/linux

[PATCH v7 0/2] iommu/arm-smmu: hard iova_to_phys

v1..v2: - Renamed one of the iopoll macros to use the more standard `_atomic' suffix - Removed some convenience iopoll wrappers to encourage explicitness Matt Wagantall (1): iopoll: Introduce memory-mapped IO polling macros Mitchel Humpherys (1): iommu/arm-smmu: add support

Re: [PATCH v7 1/2] iopoll: Introduce memory-mapped IO polling macros

On Thu, Oct 30 2014 at 05:00:23 AM, Arnd Bergmann a...@arndb.de wrote: On Thursday 30 October 2014 11:41:00 Will Deacon wrote: + +#define readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \ + readx_poll_timeout(readl, addr, val, cond, delay_us, timeout_us) + +#define

Re: [PATCH 5/6] iommu/arm-smmu: support buggy implementations with invalidate-on-map

On Wed, Nov 12 2014 at 10:26:43 AM, Will Deacon will.dea...@arm.com wrote: Hi Mitch, On Wed, Aug 13, 2014 at 01:51:38AM +0100, Mitchel Humpherys wrote: Add a workaround for some buggy hardware that requires a TLB invalidate operation to occur at map time. Activate the feature with the qcom

Re: [PATCH 5/6] iommu/arm-smmu: support buggy implementations with invalidate-on-map

On Thu, Nov 13 2014 at 01:48:26 AM, Will Deacon will.dea...@arm.com wrote: Ha, damn, then I don't have a user of the shiny new quirks field I added! I don't think I'll go as far as removing it altogether though... I'm sure we'll be making liberal use of that field soon enough ;) -Mitch --

[PATCH RESEND v8] iopoll: Introduce memory-mapped IO polling macros

Reding thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Cc: Arnd Bergmann a...@arndb.de Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- Sorry for any confusion regarding the genesis of this patch. Let me try to clarify

[PATCH RESEND v8] iopoll: Introduce memory-mapped IO polling macros

Reding thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Cc: Arnd Bergmann a...@arndb.de Cc: Andrew Morton a...@linux-foundation.org Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- This patch was originally part of a series [1

Re: [PATCH RESEND v8] iopoll: Introduce memory-mapped IO polling macros

On Mon, Nov 24 2014 at 04:53:19 PM, Elliott, Robert (Server Storage) elli...@hp.com wrote: -Original Message- From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- ow...@vger.kernel.org] On Behalf Of Mitchel Humpherys Sent: Monday, 24 November, 2014 2:15 PM ... From: Matt

Re: [PATCH 2/4] iommu: add ARM LPAE page table allocator

On Thu, Nov 27 2014 at 03:51:16 AM, Will Deacon will.dea...@arm.com wrote: A number of IOMMUs found in ARM SoCs can walk architecture-compatible page tables. This patch adds a generic allocator for Stage-1 and Stage-2 v7/v8 long-descriptor page tables. 4k, 16k and 64k pages are supported,

[PATCH v9] iopoll: Introduce memory-mapped IO polling macros

Reding thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Cc: Arnd Bergmann a...@arndb.de Cc: Andrew Morton a...@linux-foundation.org Cc: Robert Elliott elli...@hp.com Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- v8..v9

Re: [PATCH v9] iopoll: Introduce memory-mapped IO polling macros

On Mon, Dec 15 2014 at 03:31:20 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: From: Matt Wagantall ma...@codeaurora.org It is sometimes necessary to poll a memory-mapped register until its value satisfies some condition. Introduce a family of convenience macros that do this. Tight

[PATCH v10] iopoll: Introduce memory-mapped IO polling macros

Reding thierry.red...@gmail.com Cc: Will Deacon will.dea...@arm.com Cc: Arnd Bergmann a...@arndb.de Cc: Andrew Morton a...@linux-foundation.org Cc: Robert Elliott elli...@hp.com Signed-off-by: Matt Wagantall ma...@codeaurora.org Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- v9..10

[PATCH] iommu/arm-smmu: don't touch the secure STLBIALL register

Currently we do a STLBIALL when we initialize the SMMU. However, in some configurations that register is not supposed to be touched and is marked as Secure only in the spec. Rip it out. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- drivers/iommu/arm-smmu.c | 2 -- 1 file changed

Re: [PATCH] iommu/arm-smmu: use a threaded handler for context interrupts

On Fri, Jan 23 2015 at 03:24:15 AM, Will Deacon will.dea...@arm.com wrote: Hi Mitch, On Thu, Jan 22, 2015 at 11:48:02PM +, Mitchel Humpherys wrote: Context interrupts can call domain-specific handlers which might sleep. Currently we register our handler with request_irq, so our handler

Re: [PATCH] iommu/arm-smmu: use a threaded handler for context interrupts

On Wed, Feb 04 2015 at 03:33:05 AM, Will Deacon will.dea...@arm.com wrote: On Mon, Feb 02, 2015 at 08:10:02PM +, Mitchel Humpherys wrote: On Wed, Jan 28 2015 at 04:07:39 AM, Will Deacon will.dea...@arm.com wrote: With a shared handler (e.g. a bunch of context banks have the same IRQ

Re: [PATCH] iommu/arm-smmu: use a threaded handler for context interrupts

On Wed, Jan 28 2015 at 04:07:39 AM, Will Deacon will.dea...@arm.com wrote: On Fri, Jan 23, 2015 at 10:33:20PM +, Mitchel Humpherys wrote: On Fri, Jan 23 2015 at 03:24:15 AM, Will Deacon will.dea...@arm.com wrote: On Thu, Jan 22, 2015 at 11:48:02PM +, Mitchel Humpherys wrote: Context

Re: [PATCH v10] iopoll: Introduce memory-mapped IO polling macros

On Tue, Dec 16 2014 at 01:45:27 AM, Will Deacon will.dea...@arm.com wrote: On Mon, Dec 15, 2014 at 11:47:23PM +, Mitchel Humpherys wrote: From: Matt Wagantall ma...@codeaurora.org It is sometimes necessary to poll a memory-mapped register until its value satisfies some condition

[PATCH] iommu/arm-smmu: use a threaded handler for context interrupts

the way for doing things like enabling clocks within our interrupt handler. Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- drivers/iommu/arm-smmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index

Re: [PATCH v7 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

On Tue, Jan 20 2015 at 06:16:43 AM, Will Deacon will.dea...@arm.com wrote: Hey Mitch, On Wed, Oct 29, 2014 at 09:13:40PM +, Mitchel Humpherys wrote: Currently, we provide the iommu_ops.iova_to_phys service by doing a table walk in software to translate IO virtual addresses to physical

Re: [PATCH] iommu/arm-smmu: don't touch the secure STLBIALL register

On Tue, Jan 06 2015 at 06:15:07 AM, Will Deacon will.dea...@arm.com wrote: /* Invalidate the TLB, just in case */ -writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); writel_relaxed(0, gr0_base +

Re: [PATCH] iommu/arm-smmu: don't touch the secure STLBIALL register

On Tue, Jan 06 2015 at 02:35:28 PM, Rob Herring robherri...@gmail.com wrote: On Tue, Jan 6, 2015 at 2:16 PM, Mitchel Humpherys mitch...@codeaurora.org wrote: On Tue, Jan 06 2015 at 06:15:07 AM, Will Deacon will.dea...@arm.com wrote: /* Invalidate the TLB, just in case

Re: [PATCH] iommu/arm-smmu: don't touch the secure STLBIALL register

On Wed, Jan 07 2015 at 10:04:20 AM, Will Deacon will.dea...@arm.com wrote: On Wed, Jan 07, 2015 at 05:52:46PM +, Mitchel Humpherys wrote: On Wed, Jan 07 2015 at 02:13:00 AM, Will Deacon will.dea...@arm.com wrote: On Tue, Jan 06, 2015 at 11:30:49PM +, Mitchel Humpherys wrote: On Tue

Re: [PATCH] iommu/arm-smmu: don't touch the secure STLBIALL register

On Wed, Jan 07 2015 at 02:13:00 AM, Will Deacon will.dea...@arm.com wrote: On Tue, Jan 06, 2015 at 11:30:49PM +, Mitchel Humpherys wrote: On Tue, Jan 06 2015 at 02:35:28 PM, Rob Herring robherri...@gmail.com wrote: On Tue, Jan 6, 2015 at 2:16 PM, Mitchel Humpherys mitch

Re: [PATCH 2/5] iommu/mediatek: Add mt8173 IOMMU driver

On Fri, Mar 06 2015 at 02:48:17 AM, yong...@mediatek.com wrote: From: Yong Wu yong...@mediatek.com This patch adds support for mediatek m4u (MultiMedia Memory Management Unit). Currently this only supports m4u gen 2 with 2 levels of page table on mt8173. [...] +static int

[PATCH] iommu/arm-smmu: fix leak in arm_smmu_flush_pgtable

following the map. Without this, eventually swiotlb runs out of memory and starts printing things like: [ 35.545076] arm-smmu d0.arm,smmu: swiotlb buffer is full (sz: 128 bytes) Signed-off-by: Mitchel Humpherys mitch...@codeaurora.org --- drivers/iommu/arm-smmu.c | 9 +++-- 1 file

Re: [PATCH] iommu/arm-smmu: fix leak in arm_smmu_flush_pgtable

On Thu, Mar 05 2015 at 02:38:45 AM, Robin Murphy robin.mur...@arm.com wrote: Hi Mitch, On 05/03/15 00:18, Mitchel Humpherys wrote: We're currently mapping a page in arm_smmu_flush_pgtable without ever unmapping it. Fix this by calling dma_unmap_page on the returned dma address. Since

Re: [PATCH] iommu/arm-smmu: Only return IRQ_NONE if FSR is not set

On Mon, Oct 05 2015 at 03:24:03 PM, Will Deacon <will.dea...@arm.com> wrote: > Hi Mitch, > > On Sat, Sep 26, 2015 at 01:12:05AM +0100, Mitchel Humpherys wrote: >> Currently we return IRQ_NONE from the context fault handler if the FSR >> doesn't actually have t

[PATCH] iommu/arm-smmu: Only return IRQ_NONE if FSR is not set

that the interrupt wasn't for this device if the client doesn't register a handler isn't exactly accurate. Fix this by returning IRQ_HANDLED even if the client doesn't register a handler. Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> --- drivers/iommu/arm-smmu.c | 2 +- 1 file c

Re: How to keep PCI-e endpoints and RCs in distinct IOMMU groups?

On Wed, May 25 2016 at 08:45:58 PM, Alex Williamson wrote: >> Why do we do that? If the devices have different BDFs can't we safely >> say that they're protected from peer-to-peer DMA (assuming no DMA >> aliasing quirks)? Even as I write that out it seems wrong

Re: How to keep PCI-e endpoints and RCs in distinct IOMMU groups?

On Thu, May 26 2016 at 11:58:53 AM, Robin Murphy <robin.mur...@arm.com> wrote: > Hey Mitch, > > On 26/05/16 01:26, Mitchel Humpherys wrote: >> Hey there, >> >> We're experiencing an issue with IOMMU groups and PCI-e devices. The >> system in question ha

How to keep PCI-e endpoints and RCs in distinct IOMMU groups?

Hey there, We're experiencing an issue with IOMMU groups and PCI-e devices. The system in question has a WLAN DMA master behind a PCI-e root complex which is, in turn, behind an IOMMU. There are no there devices behind the RC. This is on an ARM platform using the arm-smmu and pci-msm drivers

Re: [PATCH 1/2] iommu: Support dynamic pgsize_bitmap

On Wed, Apr 06 2016 at 11:47:19 AM, Robin Murphy wrote: > How would you handle said restriction of page sizes under this scheme? I have a custom io-pgtable implementation that gets wired up based on an IOMMU domain attribute, which is set by yet another custom DMA mapper.

Re: [PATCH 1/2] iommu: Support dynamic pgsize_bitmap

On Thu, Apr 07 2016 at 12:29:59 PM, Mitchel Humpherys <mitch...@codeaurora.org> wrote: >> I'll clean up what I have and try to get it posted this afternoon so >> we can compare. > > Cool, I have some comments that I'll leave over there. Never mind, my comments weren't rel

[PATCH 1/2] iommu: Support dynamic pgsize_bitmap

to the iommu_ops which can optionally be used by the driver to return a domain-specific pgsize_bitmap. Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> --- drivers/iommu/iommu.c | 28 +++- include/linux/iommu.h | 3 +++ 2 files changed, 22 insertions

[PATCH 2/2] iommu/arm-smmu: Implement .get_pgsize_bitmap for domain

. Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> --- drivers/iommu/arm-smmu.c | 21 ++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 2409e3bd3df2..a1b0f542d5ca 100644 --- a/drivers/iom

Re: [PATCH v3 0/6] Add support for privileged mappings

On Fri, Jul 22 2016 at 05:51:07 PM, Will Deacon <will.dea...@arm.com> wrote: > On Tue, Jul 19, 2016 at 01:36:49PM -0700, Mitchel Humpherys wrote: >> The following patch to the ARM SMMU driver: >> >> commit d346180e70b91b3d5a1ae7e5603e65593d4622bc >>

Re: [PATCH v3 0/6] Add support for privileged mappings

On Mon, Jul 25 2016 at 10:50:13 AM, Will Deacon <will.dea...@arm.com> wrote: > On Fri, Jul 22, 2016 at 01:39:45PM -0700, Mitchel Humpherys wrote: >> On Fri, Jul 22 2016 at 05:51:07 PM, Will Deacon <will.dea...@arm.com> wrote: >> > On Tue, Jul 19, 2016 at 01:36:49PM

[PATCH v4 6/6] Revert "iommu/arm-smmu: Treat all device transactions as unprivileged"

This reverts commit d346180e70b9 ("iommu/arm-smmu: Treat all device transactions as unprivileged") since some platforms actually make use of privileged transactions. Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> --- Notes: v2..v3 - Moved to the e

[PATCH v4 0/6] Add support for privileged mappings

privileged mappings work, and use that in the pl330 driver (suggested by Will). Jeremy Gebben (1): iommu/io-pgtable-arm: add support for the IOMMU_PRIV flag Mitchel Humpherys (5): iommu: add IOMMU_PRIV attribute common: DMA-mapping: add DMA_ATTR_PRIVILEGED attribute arm64/dma

[PATCH v4 5/6] dmaengine: pl330: Make sure microcode is privileged

the DMA_ATTR_PRIVILEGED attribute, which will ensure that the microcode IOMMU mapping is only accessible to the privileged level. Cc: Dan Williams <dan.j.willi...@intel.com> Cc: Jassi Brar <jassi.b...@samsung.com> Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> ---

[PATCH v4 3/6] common: DMA-mapping: add DMA_ATTR_PRIVILEGED attribute

e to the DMA-mapping subsystem that the buffer is fully accessible at the elevated privilege level (and ideally inaccessible or at least read-only at the lesser-privileged levels). Cc: linux-...@vger.kernel.org Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> --- Notes: v3..v4

[PATCH v4 2/6] iommu/io-pgtable-arm: add support for the IOMMU_PRIV flag

From: Jeremy Gebben Allow the creation of privileged mode mappings, for stage 1 only. Signed-off-by: Jeremy Gebben --- Notes: v2..v3 - Use existing bit definitions. drivers/iommu/io-pgtable-arm.c | 5 - 1 file changed, 4

[PATCH v4 1/6] iommu: add IOMMU_PRIV attribute

Add the IOMMU_PRIV attribute, which is used to indicate privileged mappings. Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> --- Notes: v2..v3 - Added comment include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/iommu.h b/i

[PATCH v4 4/6] arm64/dma-mapping: Implement DMA_ATTR_PRIVILEGED

The newly added DMA_ATTR_PRIVILEGED is useful for creating mappings that are only accessible to privileged DMA engines. Implement it in dma-iommu.c so that the ARM64 DMA IOMMU mapper can make use of it. Signed-off-by: Mitchel Humpherys <mitch...@codeaurora.org> --- Notes:

Re: [PATCH v4 4/6] arm64/dma-mapping: Implement DMA_ATTR_PRIVILEGED

On Tue, Jul 26 2016 at 04:05:17 PM, Robin Murphy wrote: > + if (attrs & DMA_ATTR_PRIVILEGED) > + prot |= IOMMU_PRIV; > + > > then drop the rest of the changes to the switch statement below. It's > taken me an embarrassingly long time to work out why things

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