On Sat, May 12, 2018 at 06:25:13PM +0530, valmiki wrote:
Hi All,
What is the difference between IOVA address and bus address
when SMMU is enabled ?
Is IOVA address term used only when hypervisor is present ?
IOVA = IO virtual address. IOVA is the term normally used to describe
the address
Hi All,
What is the difference between IOVA address and bus address
when SMMU is enabled ?
Is IOVA address term used only when hypervisor is present ?
Regards,
Valmiki
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ion are carried out in PASID flow w.r.t address and size?
Regards,
Valmiki
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On 9/13/2017 6:50 AM, Jean-Philippe Brucker wrote:
Hi Valmiki,
On 12/09/17 19:01, valmiki wrote:
Hi, as per VFIO documentation i see that we need to see
"/sys/bus/pci/devices/:06:0d.0/iommu_group" in order to find group
in which PCI bus is attached.
But as per drivers/pci/p
showing these paths i.e show specific to each bus, does
SMMU need any particular confguration (we have SMMUv2) ?
Do we need any specific kernel configuration ?
Regards,
Valmiki
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On 8/7/2017 4:01 PM, Jean-Philippe Brucker wrote:
On 05/08/17 06:14, valmiki wrote:
[...]
Hi Jean, Thanks a lot, now i understood the flow. From vfio kernel
documentation we fill vaddr and iova in struct vfio_iommu_type1_dma_map
and pass them to VFIO. But if we use dynamic allocation
On 8/2/2017 12:10 AM, Jean-Philippe Brucker wrote:
On 01/08/17 18:38, valmiki wrote:
[...]
So i digged through your patches and i understood that using BIND ioctls
satge-1 translations are setup in SMMU for an application.
If we use VFIO_IOMMU_MAP/UNMAP_DMA ioctls they are setting up stage-2
On 8/1/2017 1:56 PM, Jean-Philippe Brucker wrote:
Hi Valmiki,
Sorry for the delay, I was away last week.
On 22/07/17 03:05, valmiki wrote:
On 7/12/2017 10:18 PM, Jean-Philippe Brucker wrote:
On 12/07/17 17:27, valmiki wrote:
On 7/11/2017 4:26 PM, Jean-Philippe Brucker wrote:
Hi Valmiki
On 7/12/2017 10:18 PM, Jean-Philippe Brucker wrote:
On 12/07/17 17:27, valmiki wrote:
On 7/11/2017 4:26 PM, Jean-Philippe Brucker wrote:
Hi Valmiki,
On 09/07/17 04:15, valmiki wrote:
Hi,
In SMMUv3 architecture document i see "PASIDs are optional,
configurable, and of a size deter
On 7/11/2017 4:26 PM, Jean-Philippe Brucker wrote:
Hi Valmiki,
On 09/07/17 04:15, valmiki wrote:
Hi,
In SMMUv3 architecture document i see "PASIDs are optional,
configurable, and of a size determined by the minimum
of the endpoint".
So if PASID's are optional and not supported b
On 7/11/2017 1:01 AM, Jerome Glisse wrote:
On Sun, Jul 09, 2017 at 08:45:57AM +0530, valmiki wrote:
Hi,
In SMMUv3 architecture document i see "PASIDs are optional,
configurable, and of a size determined by the minimum
of the endpoint".
So if PASID's are optional and not supported b
Hi,
In SMMUv3 architecture document i see "PASIDs are optional,
configurable, and of a size determined by the minimum
of the endpoint".
So if PASID's are optional and not supported by PCIe end point, how SVM
can be achieved ?
It cannot be inferred from that statement that PASID support is not
ss virtual address is
obtained ?
Regards,
Valmiki
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Hi All,
We have drivers/vfio/vfio_iommu_type1.c. what is type1 iommu? Is it
w.r.t vfio layer it is being referred?
Is there type 2 IOMMU w.r.t vfio? If so what is it?
Regards,
Valmiki
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