On Mon, Apr 01, 2013 at 02:45:18PM +0900, Takao Indoh wrote:
Current flow on kdump boot
enable_IR
intel_enable_irq_remapping
iommu_disable_irq_remapping == IRES/QIES/TES disabled here
dmar_disable_qi == do nothing
dmar_enable_qi == QIES enabled
On Wed, Mar 27, 2013 at 06:51:34PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add IOMMU event log injection interface for testing event flag decoding logic.
This interface allows users to specify device id, event flag, and event types
On 4/2/2013 9:33 AM, Joerg Roedel wrote:
Hi Suravee,
On Wed, Mar 27, 2013 at 06:51:23PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This
On Tue, Apr 02, 2013 at 04:33:36PM +0200, Joerg Roedel wrote:
Hi Suravee,
On Wed, Mar 27, 2013 at 06:51:23PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD
On 2 Apr 2013 15:37, Pat Erley pat-l...@erley.org wrote:
On 03/07/2013 09:35 PM, Andrew Cooks wrote:
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
+/* Table of multiple (ghost) source functions. This is similar to the
+ * translated sources above, but with the following
On Tue, Apr 02, 2013 at 04:40:37PM +0200, Borislav Petkov wrote:
While you guys are at it, can someone fix this too pls (ASUS board with
a PD on it).
[0.220342] [Firmware Bug]: AMD-Vi: IOAPIC[9] not in IVRS table
[0.220398] [Firmware Bug]: AMD-Vi: IOAPIC[10] not in IVRS table
[
On Fri, Mar 29, 2013 at 01:23:59AM +0530, Varun Sethi wrote:
Add an iommu domain pointer to device (powerpc) archdata. Devices
are attached to iommu domains and this pointer provides a mechanism
to correlate between a device and the associated iommu domain. This
field is set when a device is
-Original Message-
From: Sethi Varun-B16395
Sent: Thursday, March 28, 2013 2:54 PM
To: j...@8bytes.org; Yoder Stuart-B08248; Wood Scott-B07421;
iommu@lists.linux-foundation.org; linuxppc-
d...@lists.ozlabs.org; linux-ker...@vger.kernel.org;
ga...@kernel.crashing.org;
On Tue, Apr 02, 2013 at 05:03:04PM +0200, Joerg Roedel wrote:
On Tue, Apr 02, 2013 at 04:40:37PM +0200, Borislav Petkov wrote:
While you guys are at it, can someone fix this too pls (ASUS board with
a PD on it).
[0.220342] [Firmware Bug]: AMD-Vi: IOAPIC[9] not in IVRS table
[
On 4/2/2013 10:29 AM, Borislav Petkov wrote:
On Tue, Apr 02, 2013 at 05:03:04PM +0200, Joerg Roedel wrote:
On Tue, Apr 02, 2013 at 04:40:37PM +0200, Borislav Petkov wrote:
While you guys are at it, can someone fix this too pls (ASUS board with
a PD on it).
[0.220342] [Firmware Bug]:
On 03/07/2013 09:35 PM, Andrew Cooks wrote:
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
+/* Table of multiple (ghost) source functions. This is similar to the
+ * translated sources above, but with the following differences:
+ * 1. the device may use multiple functions as DMA sources,
On 04/02/2013 10:50 AM, Andrew Cooks wrote:
On 2 Apr 2013 15:37, Pat Erley pat-l...@erley.org
mailto:pat-l...@erley.org wrote:
On 03/07/2013 09:35 PM, Andrew Cooks wrote:
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
+/* Table of multiple (ghost) source functions. This is
On Tue, Apr 02, 2013 at 05:29:56PM +0200, Borislav Petkov wrote:
On Tue, Apr 02, 2013 at 05:03:04PM +0200, Joerg Roedel wrote:
Good luck trying to get ASUS to fix anything in their BIOS :(.
Hmm...
Can't we detect the SB IOAPIC some other way in this case?
I can certainly write a patch that
On Tue, Apr 02, 2013 at 10:41:25AM -0500, Suthikulpanit, Suravee wrote:
Turning this into WARN_ON() at this point might break a lot of
systems currently out in the field. However, users can always
switching to use intremap=off but this might not be obvious.
A WARN_ON doesn't break systems, it
Cc'ing Alex Williamson
Alex, can you please review the iommu-group part of this patch?
My comments so far are below:
On Fri, Mar 29, 2013 at 01:24:02AM +0530, Varun Sethi wrote:
+config FSL_PAMU
+ bool Freescale IOMMU support
+ depends on PPC_E500MC
+ select IOMMU_API
+
On Fri, Mar 29, 2013 at 01:23:57AM +0530, Varun Sethi wrote:
This patchset provides the Freescale PAMU (Peripheral Access Management Unit)
driver
and the corresponding IOMMU API implementation. PAMU is the IOMMU present on
Freescale
QorIQ platforms. PAMU can authorize memory access, remap
On 04/02/2013 11:47 AM, Pat Erley wrote:
On 04/02/2013 10:50 AM, Andrew Cooks wrote:
On 2 Apr 2013 15:37, Pat Erley pat-l...@erley.org
mailto:pat-l...@erley.org wrote:
On 03/07/2013 09:35 PM, Andrew Cooks wrote:
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
+/* Table of
Alex,
We are in the process of implementing vfio-pci support for the Freescale
IOMMU (PAMU). It is an aperture/window-based IOMMU and is quite different
than x86, and will involve creating a 'type 2' vfio implementation.
For each device's DMA mappings, PAMU has an overall aperture and a number
-Original Message-
From: Joerg Roedel [mailto:j...@8bytes.org]
Sent: Tuesday, April 02, 2013 9:53 PM
To: Sethi Varun-B16395
Cc: Yoder Stuart-B08248; Wood Scott-B07421; iommu@lists.linux-
foundation.org; linuxppc-...@lists.ozlabs.org; linux-
ker...@vger.kernel.org;
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
Signed-off-by: Suravee Suthikulpanit
Hi Stuart,
On Tue, 2013-04-02 at 17:32 +, Yoder Stuart-B08248 wrote:
Alex,
We are in the process of implementing vfio-pci support for the Freescale
IOMMU (PAMU). It is an aperture/window-based IOMMU and is quite different
than x86, and will involve creating a 'type 2' vfio
On Tue, Apr 2, 2013 at 2:39 PM, Scott Wood scottw...@freescale.com wrote:
On 04/02/2013 12:32:00 PM, Yoder Stuart-B08248 wrote:
Alex,
We are in the process of implementing vfio-pci support for the Freescale
IOMMU (PAMU). It is an aperture/window-based IOMMU and is quite different
than x86,
On Tue, Apr 2, 2013 at 3:32 PM, Alex Williamson
alex.william...@redhat.com wrote:
2. MSI window mappings
The more problematic question is how to deal with MSIs. We need to
create mappings for up to 3 MSI banks that a device may need to target
to generate interrupts. The Linux MSI
On 04/02/2013 03:32:17 PM, Alex Williamson wrote:
On Tue, 2013-04-02 at 17:32 +, Yoder Stuart-B08248 wrote:
2. MSI window mappings
The more problematic question is how to deal with MSIs. We need
to
create mappings for up to 3 MSI banks that a device may need to
target
to
On Tue, Apr 2, 2013 at 3:47 PM, Scott Wood scottw...@freescale.com wrote:
On 04/02/2013 03:38:42 PM, Stuart Yoder wrote:
On Tue, Apr 2, 2013 at 2:39 PM, Scott Wood scottw...@freescale.com
wrote:
On 04/02/2013 12:32:00 PM, Yoder Stuart-B08248 wrote:
Alex,
We are in the process of
On Tue, Apr 02, 2013 at 09:32:40PM +0200, Borislav Petkov wrote:
On Tue, Apr 02, 2013 at 06:33:18PM +0200, Joerg Roedel wrote:
Okay, in theory I could implement a feedback loop between timer-setup
and intremap code and try fixups until it works. But that seems not to
be worth it to work
On 04/02/2013 03:38:42 PM, Stuart Yoder wrote:
On Tue, Apr 2, 2013 at 2:39 PM, Scott Wood scottw...@freescale.com
wrote:
On 04/02/2013 12:32:00 PM, Yoder Stuart-B08248 wrote:
Alex,
We are in the process of implementing vfio-pci support for the
Freescale
IOMMU (PAMU). It is an
On Tue, 2013-04-02 at 16:08 -0500, Stuart Yoder wrote:
On Tue, Apr 2, 2013 at 3:57 PM, Scott Wood scottw...@freescale.com wrote:
C. Explicit mapping using normal DMA map. The last idea is that
we would introduce a new ioctl to give user-space an fd to
the MSI bank,
On 04/02/2013 04:08:27 PM, Stuart Yoder wrote:
On Tue, Apr 2, 2013 at 3:57 PM, Scott Wood scottw...@freescale.com
wrote:
This could also be done as another type2 ioctl extension.
Again, what is type2, specifically? If someone else is adding
their own
IOMMU that is kind of, sort of like
On Tue, Apr 02, 2013 at 02:05:14PM -0500, Suthikulpanit, Suravee wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
+static const char * const _type_field_encodings[] = {
+ /* 00 */Reserved,
+ /* 01 */Master Abort,
+ /* 10 */Target Abort,
+ /* 11 */Data Error,
On 04/02/2013 04:16:11 PM, Alex Williamson wrote:
On Tue, 2013-04-02 at 15:54 -0500, Stuart Yoder wrote:
The number of windows is always power of 2 (and max is 256). And
to reduce
PAMU cache pressure you want to use the fewest number of windows
you can.So, I don't see practically how
On 04/02/2013 04:38:45 PM, Alex Williamson wrote:
On Tue, 2013-04-02 at 16:08 -0500, Stuart Yoder wrote:
On Tue, Apr 2, 2013 at 3:57 PM, Scott Wood
scottw...@freescale.com wrote:
C. Explicit mapping using normal DMA map. The last idea
is that
we would introduce a new ioctl
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE information in
additional cases.
This is an example:
AMD-Vi: Event logged
On Tue, Apr 2, 2013 at 11:18 AM, Joerg Roedel j...@8bytes.org wrote:
+ panic(\n);
A kernel panic seems like an over-reaction to an access violation.
We have no way to determining what code caused the violation, so we
can't just kill the process. I agree it seems like overkill, but what
On Tue, 2013-04-02 at 17:13 -0500, Scott Wood wrote:
On 04/02/2013 04:16:11 PM, Alex Williamson wrote:
On Tue, 2013-04-02 at 15:54 -0500, Stuart Yoder wrote:
The number of windows is always power of 2 (and max is 256). And
to reduce
PAMU cache pressure you want to use the fewest
On Tue, 2013-04-02 at 17:44 -0500, Scott Wood wrote:
On 04/02/2013 04:32:04 PM, Alex Williamson wrote:
On Tue, 2013-04-02 at 15:57 -0500, Scott Wood wrote:
On 04/02/2013 03:32:17 PM, Alex Williamson wrote:
On x86 the interrupt remapper handles this transparently when MSI
is enabled
On Tue, 2013-04-02 at 17:50 -0500, Scott Wood wrote:
On 04/02/2013 04:38:45 PM, Alex Williamson wrote:
On Tue, 2013-04-02 at 16:08 -0500, Stuart Yoder wrote:
On Tue, Apr 2, 2013 at 3:57 PM, Scott Wood
scottw...@freescale.com wrote:
C. Explicit mapping using normal DMA map. The
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 7:23 AM
To: Timur Tabi
Cc: Joerg Roedel; Sethi Varun-B16395; lkml; Kumar Gala; Yoder Stuart-
B08248; iommu@lists.linux-foundation.org; Benjamin Herrenschmidt;
linuxppc-...@lists.ozlabs.org
Subject: Re:
Kumar/Ben,
Any comments?
(Had checked with Ben (on IRC) sometime back, he was fine with this patch)
Regards
Varun
-Original Message-
From: Joerg Roedel [mailto:j...@8bytes.org]
Sent: Tuesday, April 02, 2013 8:39 PM
To: Sethi Varun-B16395
Cc: Yoder Stuart-B08248; Wood Scott-B07421;
-Original Message-
From: Joerg Roedel [mailto:j...@8bytes.org]
Sent: Tuesday, April 02, 2013 8:40 PM
To: Sethi Varun-B16395
Cc: Yoder Stuart-B08248; Wood Scott-B07421; iommu@lists.linux-
foundation.org; linuxppc-...@lists.ozlabs.org; linux-
ker...@vger.kernel.org;
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