2bit memory writes and as such the SMMU
performs a 32bit write in response to the MSI. If so then what is different
with the Hi16xx that causes a problem? Have you been able to able to adjust
the layout of the arm_smmu_device struct to demonstrate this?
Thanks,
Andrew Murray
>
> It's good to ex
m v4, but I've dropped the
> previous tested-by since there are a fair few subtle changes in how it's
> integrated. Patches are based on Will's iommu/devel branch plus my "Fix
> big-endian CMD_SYNC writes" patch.
Reviewed-by: Andrew Murray
Thanks,
Andrew Murray
>
> Robin.
>
> - },
You indicated that "Patches are based on Will's iommu/devel branch plus my
"Fix big-endian CMD_SYNC writes" patch." - However your v2 of that patch didn't
include this cpu_to_le32 hunk.
Reviewed-by: Andrew Murray
Thanks,
Andrew Murray
>
Remove unnecessary code and license text.
Andrew Murray (2):
iommu/arm-smmu-v3: Add SPDX header
iommu/arm-smmu-v3: Remove unnecessary wrapper function
drivers/iommu/arm-smmu-v3.c | 25 +
1 file changed, 5 insertions(+), 20 deletions(-)
--
2.7.4
Simplify the code by removing an unnecessary wrapper function.
This was left behind by commit 2f657add07a8
("iommu/arm-smmu-v3: Specialise CMD_SYNC handling")
Signed-off-by: Andrew Murray
---
drivers/iommu/arm-smmu-v3.c | 12
1 file changed, 4 insertions(+), 8 deletion
Replace license text with SDPX header
Signed-off-by: Andrew Murray
---
drivers/iommu/arm-smmu-v3.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index db402e8..c7bd18e 100644
--- a/drivers/iommu/arm
On Tue, Nov 19, 2019 at 12:49:24PM +0100, Nicolas Saenz Julienne wrote:
> On Tue, 2019-11-19 at 11:18 +0000, Andrew Murray wrote:
> > On Tue, Nov 12, 2019 at 04:59:19PM +0100, Nicolas Saenz Julienne wrote:
> > > This series aims at providing support for Raspberry Pi 4's PCI
