-> page -> phys_addr)...
On 08/10/2018 09:02 AM, Kit Chow wrote:
Turns out there is no dma_map_resource routine on x86. get_dma_ops
returns intel_dma_ops which has map_resource pointing to NULL.
(gdb) p intel_dma_ops
$7 = {alloc = 0x8150f310 ,
free = 0x8150ec20 ,
mmap
trs);
debug_dma_map_page(dev, virt_to_page(ptr),
offset_in_page(ptr), size,
dir, addr, true);
return addr;
}
On 08/09/2018 04:00 PM, Kit Chow wrote:
On 08/09/2018 03:50 PM, Logan Gunthorpe wrote:
On 09/08/18 04:48 PM,
Success!
I've implemented a new intel_map_resource (and intel_unmap_resource)
routine which is called by dma_map_resource. As mentioned previously,
the primary job of dma_map_resource/intel_map_resource is to call the
intel iommu internal mapping routine (__intel_map_single) without
the virt_to_page code path. Does anyone have any ideas what
happended to it?
Kit
On 08/13/2018 08:21 AM, Kit Chow wrote:
On 08/13/2018 07:59 AM, Robin Murphy wrote:
On 13/08/18 15:23, Kit Chow wrote:
On 08/10/2018 07:10 PM, Logan Gunthorpe wrote:
On 10/08/18 06:53 PM, Kit Chow wrote:
On 08/13/2018 04:39 PM, Logan Gunthorpe wrote:
On 13/08/18 05:30 PM, Kit Chow wrote:
In arch/x86/include/asm/page.h, there is the following comment in
regards to validating the virtual address.
/*
* virt_to_page(kaddr) returns a valid pointer if and only if
* virt_addr_valid(kaddr
from the
virt_to_page code path. Does anyone have any ideas what happended to it?
Kit
(Resending, earlier message tagged as containing html subpart)
On 08/13/2018 08:21 AM, Kit Chow wrote:
On 08/13/2018 07:59 AM, Robin Murphy wrote:
On 13/08/18 15:23, Kit Chow wrote:
On 08/10/2018 07:10 PM,
On 08/09/2018 02:36 PM, Logan Gunthorpe wrote:
On 09/08/18 03:31 PM, Eric Pilmore wrote:
On Thu, Aug 9, 2018 at 12:35 PM, Logan Gunthorpe wrote:
Hey,
On 09/08/18 12:51 PM, Eric Pilmore wrote:
Was wondering if anybody here has used IOAT DMA engines with an
IOMMU turned on (Xeon based
On 08/16/2018 10:21 AM, Logan Gunthorpe wrote:
On 16/08/18 11:16 AM, Kit Chow wrote:
I only have access to intel hosts for testing (and possibly an AMD
host currently collecting dust) and am not sure how to go about getting
the proper test coverage for other architectures.
Well, I thought
On 08/13/2018 07:59 AM, Robin Murphy wrote:
On 13/08/18 15:23, Kit Chow wrote:
On 08/10/2018 07:10 PM, Logan Gunthorpe wrote:
On 10/08/18 06:53 PM, Kit Chow wrote:
I was able to finally succeed in doing the dma transfers over ioat
only
when prot has DMA_PTE_WRITE set by setting
On 08/10/2018 07:10 PM, Logan Gunthorpe wrote:
On 10/08/18 06:53 PM, Kit Chow wrote:
I was able to finally succeed in doing the dma transfers over ioat only
when prot has DMA_PTE_WRITE set by setting the direction to either
DMA_FROM_DEVICE or DMA_BIDIRECTIONAL. Any ideas if the prot settings
On 08/09/2018 03:40 PM, Jiang, Dave wrote:
-Original Message-
From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-ow...@vger.kernel.org]
On Behalf Of Kit Chow
Sent: Thursday, August 9, 2018 2:48 PM
To: Logan Gunthorpe ; Eric Pilmore ; Bjorn
Helgaas
Cc: linux-...@vger.kernel.org
On 08/09/2018 03:50 PM, Logan Gunthorpe wrote:
On 09/08/18 04:48 PM, Kit Chow wrote:
Based on Logan's comments, I am very hopeful that the dma_map_resource
will make things work on the older platforms...
Well, I *think* dma_map_single() would still work. So I'm not that
confident that's
On 08/13/2018 04:50 PM, Logan Gunthorpe wrote:
On 13/08/18 05:48 PM, Kit Chow wrote:
On 08/13/2018 04:39 PM, Logan Gunthorpe wrote:
On 13/08/18 05:30 PM, Kit Chow wrote:
In arch/x86/include/asm/page.h, there is the following comment in
regards to validating the virtual address
On 08/09/2018 12:35 PM, Logan Gunthorpe wrote:
Hey,
On 09/08/18 12:51 PM, Eric Pilmore wrote:
Was wondering if anybody here has used IOAT DMA engines with an
IOMMU turned on (Xeon based system)? My specific question is really
whether it is possible to DMA (w/IOAT) to a PCI BAR address as the
On 08/09/2018 01:11 PM, Logan Gunthorpe wrote:
On 09/08/18 01:47 PM, Kit Chow wrote:
I haven't tested this scenario but my guess would be that IOAT would
indeed go through the IOMMU and the PCI BAR address would need to be
properly mapped into the IOAT's IOVA. The fact that you see DMAR
On 08/09/2018 02:11 PM, Logan Gunthorpe wrote:
On 09/08/18 02:57 PM, Kit Chow wrote:
On 08/09/2018 01:11 PM, Logan Gunthorpe wrote:
On 09/08/18 01:47 PM, Kit Chow wrote:
I haven't tested this scenario but my guess would be that IOAT would
indeed go through the IOMMU and the PCI BAR
16 matches
Mail list logo
