Re: possible dmar_init_reserved_ranges() error

2016-12-27 Thread Raj, Ashok
Hi Bjorn, On Tue, Dec 27, 2016 at 05:44:17PM -0600, Bjorn Helgaas wrote: > > dmar_init_reserved_ranges() > { > ... > for_each_pci_dev(pdev) { > for (i = 0; i < PCI_NUM_RESOURCES; i++) { > r = >resource[i]; > reserve_iova(r) > > But I assume it's possible to

Re: possible dmar_init_reserved_ranges() error

2016-12-22 Thread Raj, Ashok
Hi Bjorn On Thu, Dec 22, 2016 at 02:28:03PM -0600, Bjorn Helgaas wrote: > On Thu, Dec 22, 2016 at 05:27:14PM +0100, Joerg Roedel wrote: > > Hi Bjorn, > > > > On Mon, Dec 19, 2016 at 03:20:44PM -0600, Bjorn Helgaas wrote: > > > I have some questions about dmar_init_reserved_ranges(). On systems

Re: possible dmar_init_reserved_ranges() error

2016-12-22 Thread Raj, Ashok
, Raj, Ashok wrote: > Let me check and keep you posted if we have such platforms to make sure if > we need this considerations for _TRA. Cheers, Ashok ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/li

Re: [RFC PATCH 22/30] iommu: Bind/unbind tasks to/from devices

2017-03-03 Thread Raj, Ashok
Hi David, Good to hear back from you! On Fri, Mar 03, 2017 at 09:40:44AM +, David Woodhouse wrote: > > Intel slightly deviates from the "one PASID per process" vision too, > because it currently has a PASID allocator idr per IOMMU. That wants > making system-wide. And probably not

Re: [RFC Design Doc v3] Enable Shared Virtual Memory feature in pass-through scenarios

2017-03-01 Thread Raj, Ashok
On Wed, Mar 01, 2017 at 04:09:38PM -0500, Konrad Rzeszutek Wilk wrote: > .snip.. > > > > No. SVM is purely about sharing CPU address space with device. Command > > submission is still through kernel driver which controls rings (with SVM > > then > > you can put VA into those commands). There are

Re: [PATCH 0/4] Patches to support ring0 SVM and devtlb

2017-08-15 Thread Raj, Ashok
Hi Joerg I haven't received any update to this patchset.. Could you help get this merged through your tree? we have tested this series internally. Cheers, Ashok On Tue, Aug 08, 2017 at 01:29:26PM -0700, Ashok Raj wrote: > Hi > > Sorry for resending.. iommu list email was mistyped :-( > >

Re: Support SVM without PASID

2017-08-11 Thread Raj, Ashok
On Fri, Aug 04, 2017 at 10:42:41AM +0100, Jean-Philippe Brucker wrote: > Hi Kevin, > > > Consider the situation where a userspace driver (no virtualization) is > built in a client-server fashion: the server controls a device and spawns > new processes (clients), each sharing a context with the

Re: Does a new booting kernel by "kexec -l" need to copy IR table from previous kernel?

2017-04-27 Thread Raj, Ashok
Hi Joerg, On Thu, Apr 27, 2017 at 06:12:38PM +0200, j...@8bytes.org wrote: > On Thu, Apr 27, 2017 at 03:34:06PM +, Zhuo, Qiuxu wrote: > > It looks like the printk is misleading and it’s nothing actually > > failed, but just it isn’t copying if the new kernel is not a kdump > > kernel. > >

Re: [PATCH 1/2] PCI: Save properties required to handle FLR for replay purposes.

2017-05-25 Thread Raj, Ashok
> > Cc: iommu@lists.linux-foundation.org > > > > Signed-off-by: CQ Tang <cq.t...@intel.com> > > Signed-off-by: Ashok Raj <ashok@intel.com> > > --- > > drivers/pci/ats.c | 65 > > + > >

Re: [PATCH 1/2] PCI: Save properties required to handle FLR for replay purposes.

2017-05-30 Thread Raj, Ashok
On Thu, May 11, 2017 at 11:50:24AM +0100, Jean-Philippe Brucker wrote: > Hi, > > On 10/05/17 19:39, Ashok Raj wrote: > > From: CQ Tang > > > > Requires: https://patchwork.kernel.org/patch/9593891 > > Since your series is likely to go in much earlier than my SVM mess, maybe >

Re: [RFC PATCH 03/20] intel_iommu: add "svm" option

2017-05-04 Thread Raj, Ashok
On Thu, May 04, 2017 at 02:28:53PM -0600, Alex Williamson wrote: > On Thu, 27 Apr 2017 18:53:17 +0800 > Peter Xu wrote: > > > On Wed, Apr 26, 2017 at 06:06:33PM +0800, Liu, Yi L wrote: > > > Expose "Shared Virtual Memory" to guest by using "svm" option. > > > Also use "svm" to

Re: [PATCH 2/2] PCI: Save properties required to handle FLR for replay purposes.

2017-05-30 Thread Raj, Ashok
aas <bhelg...@google.com> > > To: Joerg Roedel <j...@8bytes.org> > > To: linux-...@vger.kernel.org > > To: linux-ker...@vger.kernel.org > > Cc: Jean-Phillipe Brucker <jean-philippe.bruc...@arm.com> > > Cc: David Woodhouse <dw...@infradead.org> > > C

Re: [PATCH] iommu/vt-d: Fix scatterlist offset handling

2017-10-06 Thread Raj, Ashok
On Fri, Oct 06, 2017 at 04:43:09PM +0200, Joerg Roedel wrote: > On Tue, Oct 03, 2017 at 07:05:17PM +0100, Robin Murphy wrote: > > Now, there are indeed plenty of drivers and subsystems which do work on > > lists of explicitly single pages - anything doing some variant of > > "addr =

Re: [PATCH] iommu/vt-d: Fix scatterlist offset handling

2017-10-03 Thread Raj, Ashok
Hi Robin I now see your patch and it does seem to be fix the problem. On Thu, Sep 28, 2017 at 08:43:46AM -0700, Ashok Raj wrote: > Hi Robin > > > On Thu, Sep 28, 2017 at 05:59:11PM +0100, Robin Murphy wrote: > > I hope our email server hasn't got blacklisted again... Said patch is > > the top

Re: DMA error when sg->offset value is greater than PAGE_SIZE in Intel IOMMU

2017-09-25 Thread Raj, Ashok
Hi On Mon, Sep 25, 2017 at 01:11:04PM -0700, Dan Williams wrote: > On Mon, Sep 25, 2017 at 1:05 PM, Casey Leedom wrote: > > | From: Dan Williams > > | Sent: Monday, September 25, 2017 12:31 PM > > | ... > > | IIUC it looks like this has been broken

Re: DMA error when sg->offset value is greater than PAGE_SIZE in Intel IOMMU

2017-09-26 Thread Raj, Ashok
;offset and then find the pteval? attached below another cut at fixing the same problem.. if there is something obvious i missed, let me know. again.. untested :-) Cheers, Ashok Sometimes offset can be greater than 4K. vt-d needs to account for that. From: Ashok Raj <ashok@intel.com&

Re: DMA error when sg->offset value is greater than PAGE_SIZE in Intel IOMMU

2017-09-26 Thread Raj, Ashok
nother cut at fixing the same problem.. if there is something > obvious i missed, let me know. > > again.. untested :-) > > Cheers, > Ashok > > Sometimes offset can be greater than 4K. vt-d needs to account for that. > > From: Ashok Raj <ashok@intel.com> >

Re: DMA error when sg->offset value is greater than PAGE_SIZE in Intel IOMMU

2017-09-27 Thread Raj, Ashok
Hi Robin On Wed, Sep 27, 2017 at 06:18:02PM +0100, Robin Murphy wrote: > On Wed, 27 Sep 2017 16:31:04 + > Casey Leedom wrote: > > > | From: Dan Williams > > | Sent: Tuesday, September 26, 2017 9:10 AM > > | > > | On Tue, Sep 26, 2017 at 9:06

Re: [PATCH] iommu/vt-d: Fix scatterlist offset handling

2017-09-28 Thread Raj, Ashok
Hi Casey On Thu, Sep 28, 2017 at 04:17:59PM +, Casey Leedom wrote: > Thanks Robin. Harsh can certainly test your latest patch as soon as he's > back in the office tomorrow morning India time. If your patch works and is > accepted, it sounds like the commit would be important enough to

Re: DMA error when sg->offset value is greater than PAGE_SIZE in Intel IOMMU

2017-09-28 Thread Raj, Ashok
Thanks for trying that Harsh. sp_off turns of super page support. Which this mode, do you still see offsets greater than 4k? On Thu, Sep 28, 2017 at 07:08:21PM +0530, Harsh Jain wrote: > > > Today I tried with "Intel_iommu=sp_off" boot option. Traffic runs without any > error for more than

Re: [PATCH] iommu/vt-d: Fix scatterlist offset handling

2017-09-28 Thread Raj, Ashok
Hi Robin thanks.. i have no idea.. i see all the other patches from you :-) my email has decided to play games with me i suppose :-) On Thu, Sep 28, 2017 at 05:59:11PM +0100, Robin Murphy wrote: > I hope our email server hasn't got blacklisted again... Said patch is > the top of this very thread

Re: bind pasid table API

2017-09-28 Thread Raj, Ashok
Hi Jean On Thu, Sep 28, 2017 at 12:21:34PM +0100, Jean-Philippe Brucker wrote: > On 27/09/17 14:40, Joerg Roedel wrote: > > Hi, > > > > On Wed, Sep 20, 2017 at 01:09:47PM +0100, Jean-Philippe Brucker wrote: > >> For binding page tables instead of PASID tables (e.g. virtio-iommu), the > >>

Re: PROBLEM: intel_iommu=on under 4.13 breaks resume from suspend on my Thinkpad T560

2017-09-28 Thread Raj, Ashok
Hi Ronan has it worked ever with intel_iommu=on? This is on my list to look, but didn't get a chance to look into it. I suspect that after suspend, we do save some of the registers that might loose context. But the driver needs to reinitialize the uarch states again. for e.g. need to go

Re: DMA error when sg->offset value is greater than PAGE_SIZE in Intel IOMMU

2017-09-27 Thread Raj, Ashok
Hi Casey looking at the debug output i got from Harsh it still looks like a bug in the code. [ 538.284589] __domain_mapping nr_pages 0x1 [ 538.284600] __domain_mapping sg_res 0x1 sg->dma_address 0xf291000e dma len 0x38 pteval 0x3cbce3003 phys_pfn 0x3cbce3 [ 538.284604] chelsio driver -

Re: bind pasid table API

2017-09-25 Thread Raj, Ashok
On Mon, Sep 25, 2017 at 12:45:00PM +0100, Jean-Philippe Brucker wrote: [snip] > This format tells how the guest organizes its PASID tables. Depending on > 'format', the PASID table can be: > * A flat array of descriptors > * One array of 1st-level descriptors pointing to a 2nd level of >

Re: DMA error when sg->offset value is greater than PAGE_SIZE in Intel IOMMU

2017-09-25 Thread Raj, Ashok
Hi Casey Sorry, somehow didn't see this one come by. On Mon, Sep 25, 2017 at 05:46:40PM +, Casey Leedom wrote: > | From: Robin Murphy > | Sent: Wednesday, September 20, 2017 3:12 AM > | > | On 20/09/17 09:01, Herbert Xu wrote: > | > > | > Harsh Jain

Re: [PATCH 0/4] Patches to support ring0 SVM and devtlb

2017-08-21 Thread Raj, Ashok
Thanks Joerg On Fri, Aug 18, 2017 at 11:35:21AM +0200, Joerg Roedel wrote: > Hi Ashok, > > On Tue, Aug 15, 2017 at 07:59:29AM -0700, Raj, Ashok wrote: > > I haven't received any update to this patchset.. > > > > Could you help get this merged through your tree? we

Re: [PATCH v2 0/6] Intel IOMMU debugfs support

2017-11-22 Thread Raj, Ashok
Hi Alex you can add for the whole series Reviewed By: Ashok Raj <ashok@intel.com> On Wed, Nov 22, 2017 at 11:25:40AM -0800, Mehta, Sohil wrote: > Hi all, > > This series aims to add debugfs support for Intel IOMMU. It exposes IOMMU > registers, internal context and dump

Re: [PATCH 1/2] mm: Add kernel MMU notifier to manage IOTLB/DEVTLB

2017-12-14 Thread Raj, Ashok
Hi Bob On Thu, Dec 14, 2017 at 02:07:38PM +0800, Bob Liu wrote: > On 2017/12/14 11:38, Lu Baolu wrote: > We already have an existing MMU notifiers for userspace updates, > however we lack the same thing for kernel page table updates. To > >> Sorry, I didn't get which situation need

Re: [PATCH] iommu/vt-d: Fix scatterlist offset handling

2017-11-17 Thread Raj, Ashok
Hi Alex On Fri, Nov 17, 2017 at 09:18:14AM -0700, Alex Williamson wrote: > On Thu, 16 Nov 2017 13:09:33 -0800 > "Raj, Ashok" <ashok@intel.com> wrote: > > > > > > > What do we do about this? I certainly can't rip out large page support &g

Re: Intel-iommu: Possible memory corruption due to deferred iommu flush

2017-11-16 Thread Raj, Ashok
On Thu, Nov 16, 2017 at 12:20:47PM +0200, nick klingsman wrote: > * Note: Please 'CC'/Reply my email as I'm not subscribed to the list yet. > > Hi, > > During __iommu_flush_iotlb() we set the WD (WriteDrain) bit if the > iommu supports cap_write_drain(). This part of the logic exists from > day

Re: [PATCH] iommu/vt-d: Fix scatterlist offset handling

2017-11-16 Thread Raj, Ashok
Hi Alex On Thu, Nov 16, 2017 at 02:32:44PM -0700, Alex Williamson wrote: > On Wed, 15 Nov 2017 15:54:56 -0800 > Jacob Pan wrote: > > > Hi Alex and all, > > > > Just wondering if you could merge Robin's patch for the next rc. From > > all our testing, this seems

Re: Intel-iommu: Possible memory corruption due to deferred iommu flush

2017-11-16 Thread Raj, Ashok
Hi Nick On Fri, Nov 17, 2017 at 01:57:19AM +0200, nick klingsman wrote: > > Oh - now I understand the confusion. Although the subject said 'deferred' > I used the word 'Batched' in the email body. I meant 'deferred'. Not batching. > If it was only batching, than it would make sens as 'Ashok'

Re: [PATCH] iommu/vt-d: clean up pr_irq if request_threaded_irq fails

2017-12-06 Thread Raj, Ashok
if pr_irq is 0. Without these, if request_threaded_irq were > to fail the following occurs: Looks good. Reviewed-by: Ashok Raj <ashok@intel.com> Cheers, Ashok > > Cc: Alex Williamson <alex.william...@redhat.com> > Cc: Joerg Roedel <j...@8bytes.org> > Cc: Ashok

Re: [RFCv2 PATCH 01/36] iommu: Keep track of processes and PASIDs

2017-10-25 Thread Raj, Ashok
Hi Jean On Mon, Oct 23, 2017 at 01:17:07PM +0100, Jean-Philippe Brucker wrote: > On 23/10/17 12:04, Liu, Yi L wrote: > >> + idr_preload(GFP_KERNEL); > >> + spin_lock(_process_lock); > >> + pasid = idr_alloc_cyclic(_process_idr, process, domain->min_pasid, > >> +

Re: [PATCH v7 0/5] Add Intel IOMMU debugfs support

2018-02-13 Thread Raj, Ashok
Hi Joerg, On Tue, Feb 13, 2018 at 03:03:03PM +0100, Joerg Roedel wrote: > On Fri, Feb 02, 2018 at 04:49:56PM -0800, Sohil Mehta wrote: > > This series aims to add debugfs support for Intel IOMMU. It exposes IOMMU > > registers, internal context and dumps individual table entries to help debug > >

Re: [PATCH] vfio/pci: Some buggy virtual functions incorrectly report 1 for intx.

2018-08-10 Thread Raj, Ashok
On Fri, Aug 10, 2018 at 05:48:36PM +0100, Alan Cox wrote: > > The hardware isn't public yet, so can't talk about it :-(. Once this patch > > gets > > merged, will let the OSV engagement folks drive it for inclusions. We > > could mark this for stable, but i would rather wait until we know the

Re: [PATCH] vfio/pci: Some buggy virtual functions incorrectly report 1 for intx.

2018-08-09 Thread Raj, Ashok
On Thu, Aug 09, 2018 at 01:44:17PM -0600, Alex Williamson wrote: > On Thu, 9 Aug 2018 12:37:06 -0700 > Ashok Raj wrote: > > > PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions. > > > > Some SRIOV devices have some bugs in RTL and VF's end up reading 1 > > instead of 0 for the

Re: [RFC PATCH 3/7] vfio: add spimdev support

2018-08-06 Thread Raj, Ashok
On Mon, Aug 06, 2018 at 09:49:40AM -0600, Alex Williamson wrote: > On Mon, 6 Aug 2018 09:40:04 +0800 > Kenneth Lee wrote: > > > > 1. It supports thousands of processes. Take zip accelerator as an example, > > any > > application need data compression/decompression will need to interact with >

Re: [PATCH] x86/pci: Some buggy virtual functions incorrectly report 1 for intx.

2018-07-16 Thread Raj, Ashok
Hi Alex On Mon, Jul 16, 2018 at 03:17:57PM -0600, Alex Williamson wrote: > > static bool vfio_pci_nointx(struct pci_dev *pdev) > > { > > + /* > > +* Per PCI, no VF's should have INTx > > +* Simply disable it here > > +*/ > > + if (pdev->is_virtfn) > > + return true; >

Re: [PATCH v2 06/12] iommu/vt-d: Add second level page table interface

2018-09-07 Thread Raj, Ashok
On Fri, Sep 07, 2018 at 10:47:11AM +0800, Lu Baolu wrote: > > >>+ > >>+ intel_pasid_clear_entry(dev, pasid); > >>+ > >>+ if (!ecap_coherent(iommu->ecap)) { > >>+ pte = intel_pasid_get_entry(dev, pasid); > >>+ clflush_cache_range(pte, sizeof(*pte)); > >>+ } > >>+ > >>+

Re: [PATCH 1/1] iommu/vt-d: Handle memory shortage on pasid table allocation

2018-09-06 Thread Raj, Ashok
On Sat, Sep 01, 2018 at 02:24:16PM +0800, Lu Baolu wrote: > Pasid table memory allocation could return failure due to memory > shortage. Limit the pasid table size to 1MiB because current 8MiB > contiguous physical memory allocation can be hard to come by. W/o > a PASID table, the device could

Re: [RFC PATCH 0/6] Auxiliary IOMMU domains and Arm SMMUv3

2018-10-22 Thread Raj, Ashok
On Fri, Oct 19, 2018 at 07:11:52PM +0100, Jean-Philippe Brucker wrote: > This is a first prototype adding auxiliary domain support to Arm SMMUv3, > following Lu Baolu's latest proposal for IOMMU aware mediated devices > [1]. It works, but the attach() API still doesn't feel right. See (2) > below.

Re: [RFC PATCH 2/6] drivers core: Add I/O ASID allocator

2018-10-22 Thread Raj, Ashok
On Mon, Oct 22, 2018 at 12:49:47PM +0800, Lu Baolu wrote: > Hi, > > On 10/20/18 2:11 AM, Jean-Philippe Brucker wrote: > > Some devices might support multiple DMA address spaces, in particular > > those that have the PCI PASID feature. PASID (Process Address Space ID) > > allows to share process

Re: [RFC PATCH 0/6] Auxiliary IOMMU domains and Arm SMMUv3

2018-10-23 Thread Raj, Ashok
On Mon, 2018-10-22 at 17:03 +0100, Jean-Philippe Brucker wrote: > On 22/10/2018 11:07, Raj, Ashok wrote: > > > For my own convenience I've been using the SVA infrastructure > > > since > > > I already had the locking and IOMMU ops in place. The > > &g

Re: [PATCH 2/4] iommu/vt-d: Force IOMMU on for platform opt in hint

2018-11-12 Thread Raj, Ashok
On Mon, Nov 12, 2018 at 11:09:00AM -0700, Alex Williamson wrote: > On Mon, 12 Nov 2018 19:06:26 +0300 > Mika Westerberg wrote: > > > From: Lu Baolu > > > > Intel VT-d spec added a new DMA_CTRL_PLATFORM_OPT_IN_FLAG flag > > in DMAR ACPI table for BIOS to report compliance about platform > >

Re: [PATCH 3/4] iommu/vt-d: Do not enable ATS for external devices

2018-11-12 Thread Raj, Ashok
On Mon, Nov 12, 2018 at 07:06:27PM +0300, Mika Westerberg wrote: > Currently Linux automatically enables ATS (Address Translation Service) > for any device that supports it (and IOMMU is turned on). ATS is used to > accelerate DMA access as the device can cache translations locally so > there is

Re: [PATCH 2/4] iommu/vt-d: Force IOMMU on for platform opt in hint

2018-11-12 Thread Raj, Ashok
On Mon, Nov 12, 2018 at 07:06:26PM +0300, Mika Westerberg wrote: > From: Lu Baolu > > Intel VT-d spec added a new DMA_CTRL_PLATFORM_OPT_IN_FLAG flag > in DMAR ACPI table for BIOS to report compliance about platform > initiated DMA restricted to RMRR ranges when transferring control > to the OS.

Re: source-id verification failures

2018-10-05 Thread Raj, Ashok
On Thu, Oct 04, 2018 at 03:07:46PM -0700, Jacob Pan wrote: > On Thu, 4 Oct 2018 13:57:24 -0700 > Jerry Snitselaar wrote: > > > On Thu Oct 04 18, Joerg Roedel wrote: > > >Hi Jerry, > > > > > >thanks for the report. > > > > > >On Tue, Oct 02, 2018 at 10:25:29AM -0700, Jerry Snitselaar wrote: > >

Re: [PATCH V3] PCI: Enable PASID when End-to-End TLP is supported by all bridges

2018-09-26 Thread Raj, Ashok
Hi Sinan + IOMMU list. On Sat, Jun 30, 2018 at 11:24:24AM -0400, Sinan Kaya wrote: > A PCIe endpoint carries the process address space identifier (PASID) in > the TLP prefix as part of the memory read/write transaction. The address > information in the TLP is relevant only for a given PASID

Re: [PATCH] vfio/pci: Some buggy virtual functions incorrectly report 1 for intx.

2018-09-19 Thread Raj, Ashok
Hi Alex On Tue, Sep 18, 2018 at 09:59:57PM -0600, Alex Williamson wrote: > On Wed, 12 Sep 2018 10:46:19 -0700 > "Raj, Ashok" wrote: > > > On Thu, Aug 09, 2018 at 01:44:17PM -0600, Alex Williamson wrote: > > > On Thu, 9 Aug 2018 12:

Re: [PATCH] vfio/pci: Some buggy virtual functions incorrectly report 1 for intx.

2018-09-12 Thread Raj, Ashok
On Thu, Aug 09, 2018 at 01:44:17PM -0600, Alex Williamson wrote: > On Thu, 9 Aug 2018 12:37:06 -0700 > Ashok Raj wrote: > > > PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions. > > > > Some SRIOV devices have some bugs in RTL and VF's end up reading 1 > > instead of 0 for the

Re: [RFC PATCH v2 00/10] vfio/mdev: IOMMU aware mediated device

2018-09-13 Thread Raj, Ashok
On Thu, Sep 13, 2018 at 04:03:01PM +0100, Jean-Philippe Brucker wrote: > On 13/09/2018 01:19, Tian, Kevin wrote: > >>> This is proposed for architectures which support finer granularity > >>> second level translation with no impact on architectures which only > >>> support Source ID or the similar

Re: [PATCH 1/1] iommu: Bind process address spaces to devices

2019-02-28 Thread Raj, Ashok
On Thu, Feb 28, 2019 at 01:15:49PM -0800, Jacob Pan wrote: > On Thu, 28 Feb 2019 15:09:50 +0100 > Joerg Roedel wrote: > > > Hi Jacob, > > > > On Wed, Feb 27, 2019 at 01:41:29PM -0800, Jacob Pan wrote: > > > On Tue, 26 Feb 2019 12:17:43 +0100 > > > Joerg Roedel wrote: > > > > > Just trying

Re: [PATCH v1 1/1] iommu/vt-d: Enable PRI only if the device enables PASID.

2019-02-07 Thread Raj, Ashok
On Thu, Feb 07, 2019 at 09:15:24PM +, David Woodhouse wrote: > On Thu, 2019-02-07 at 13:09 -0800, Raj, Ashok wrote: > > You are right.. they are completely orthogonal. We just don't have > > a way to handle the page-requests for request without PASID's. > > > > T

Re: [PATCH v1 1/1] iommu/vt-d: Enable PRI only if the device enables PASID.

2019-02-07 Thread Raj, Ashok
On Thu, Feb 07, 2019 at 08:08:06PM +, David Woodhouse wrote: > On Thu, 2019-02-07 at 10:44 -0800, sathyanarayanan.kuppusw...@linux.intel.com > wrote: > > From: Kuppuswamy Sathyanarayanan > > > > > > Intel IOMMU Page Request Services (PRS) only works with devices which > > supports/uses

Re: [PATCH v2 2/2] iommu/vt-d: Enable PASID only if device expects PASID in PRG Response.

2019-02-13 Thread Raj, Ashok
On Wed, Feb 13, 2019 at 12:26:33AM -0800, Tian, Kevin wrote: > > > > diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c > > index 1457f931218e..af2e4a011787 100644 > > --- a/drivers/iommu/intel-iommu.c > > +++ b/drivers/iommu/intel-iommu.c > > @@ -1399,7 +1399,8 @@ static void

Re: [PATCH v1 1/2] PCI: ATS: Add function to check ATS page aligned request status.

2019-02-11 Thread Raj, Ashok
On Fri, Feb 08, 2019 at 11:49:55PM -0500, Sinan Kaya wrote: > On 2/8/2019 8:02 PM, sathyanarayanan kuppuswamy wrote: > >>This means that you should probably have some kind of version check > >>here. > > > >There is no version field in ATS v1.0 spec. Also, If I follow the history > >log in PCI

Re: Device specific pass through in host systems - discuss user interface

2019-06-10 Thread Raj, Ashok
On Mon, Jun 10, 2019 at 09:38:11PM -0700, Sai Praneeth Prakhya wrote: > Hi All, > > + Sohil and Rob Clark (as there are dropped from CC'list) > > > > > Most iommu vendor drivers have switched from per-device to per-group > > > > domain (a.k.a. default domain). So per-group pass-through mode

Re: Device specific pass through in host systems - discuss user interface

2019-06-10 Thread Raj, Ashok
Hi Sai On Sun, Jun 09, 2019 at 10:41:10PM -0700, Sai Praneeth Prakhya wrote: > > > I am working on an IOMMU driver feature that allows a user to specify > > > if the DMA from a device should be translated by IOMMU or not. > > > Presently, we support only all devices or none mode i.e. if user > >

Re: [PATCH v4 20/22] iommu/vt-d: Add bind guest PASID support

2019-07-16 Thread Raj, Ashok
Hi Eric Jacob is on sabbatical, so i'll give it my best shot :-) Yi/Kevin can jump in... On Tue, Jul 16, 2019 at 06:45:51PM +0200, Auger Eric wrote: > Hi Jacob, > > On 6/9/19 3:44 PM, Jacob Pan wrote: > > When supporting guest SVA with emulated IOMMU, the guest PASID > > table is shadowed in

Re: [RFC PATCH 0/4] Use 1st-level for DMA remapping in guest

2019-09-23 Thread Raj, Ashok
Hi Jacob On Mon, Sep 23, 2019 at 12:27:15PM -0700, Jacob Pan wrote: > > > > In VT-d 3.0, scalable mode is introduced, which offers two level > > translation page tables and nested translation mode. Regards to > > GIOVA support, it can be simplified by 1) moving the GIOVA support > > over

Re: [RFC PATCH 2/4] iommu/vt-d: Add first level page table interfaces

2019-09-23 Thread Raj, Ashok
On Mon, Sep 23, 2019 at 08:24:52PM +0800, Lu Baolu wrote: > This adds functions to manipulate first level page tables > which could be used by a scalale mode capable IOMMU unit. s/scalale/scalable > > intel_mmmap_range(domain, addr, end, phys_addr, prot) Maybe think of a different name..?

Re: [PATCH v6 01/10] iommu/vt-d: Enlightened PASID allocation

2019-10-22 Thread Raj, Ashok
On Tue, Oct 22, 2019 at 04:53:14PM -0700, Jacob Pan wrote: > From: Lu Baolu > > If Intel IOMMU runs in caching mode, a.k.a. virtual IOMMU, the > IOMMU driver should rely on the emulation software to allocate > and free PASID IDs. The Intel vt-d spec revision 3.0 defines a > register set to

Re: [PATCH v6 00/10] Nested Shared Virtual Address (SVA) VT-d support

2019-10-22 Thread Raj, Ashok
Hi Jacob On Tue, Oct 22, 2019 at 04:53:13PM -0700, Jacob Pan wrote: > Shared virtual address (SVA), a.k.a, Shared virtual memory (SVM) on Intel > platforms allow address space sharing between device DMA and applications. > SVA can reduce programming complexity and enhance security. > This series

Re: [PATCH v6 02/10] iommu/vt-d: Add custom allocator for IOASID

2019-10-22 Thread Raj, Ashok
On Tue, Oct 22, 2019 at 04:53:15PM -0700, Jacob Pan wrote: > When VT-d driver runs in the guest, PASID allocation must be > performed via virtual command interface. This patch registers a > custom IOASID allocator which takes precedence over the default > XArray based allocator. The resulting

Re: [PATCH v6 03/10] iommu/vt-d: Replace Intel specific PASID allocator with IOASID

2019-10-22 Thread Raj, Ashok
On Tue, Oct 22, 2019 at 04:53:16PM -0700, Jacob Pan wrote: > Make use of generic IOASID code to manage PASID allocation, > free, and lookup. Replace Intel specific code. > > Signed-off-by: Jacob Pan > --- > drivers/iommu/intel-iommu.c | 12 ++-- > drivers/iommu/intel-pasid.c | 36

Re: [PATCH v12 2/4] uacce: add uacce driver

2020-02-24 Thread Raj, Ashok
Hi Kenneth, sorry for waking up late on this patchset. On Wed, Jan 15, 2020 at 10:12:46PM +0800, Zhangfei Gao wrote: [... trimmed] > + > +static int uacce_fops_open(struct inode *inode, struct file *filep) > +{ > + struct uacce_mm *uacce_mm = NULL; > + struct uacce_device *uacce; > +

Re: [PATCH v1 2/2] vfio/pci: Emulate PASID/PRI capability for VFs

2020-04-08 Thread Raj, Ashok
Hi Alex On Wed, Apr 08, 2020 at 10:19:40AM -0600, Alex Williamson wrote: > On Tue, 7 Apr 2020 21:00:21 -0700 > "Raj, Ashok" wrote: > > > Hi Alex > > > > + Bjorn > > + Don > > > FWIW I can't understand why PCI SIG went different w

Re: [PATCH v1 0/2] vfio/pci: expose device's PASID capability to VMs

2020-04-16 Thread Raj, Ashok
Hi Zhao On Thu, Apr 16, 2020 at 06:12:26PM -0400, Yan Zhao wrote: > On Tue, Mar 31, 2020 at 03:08:25PM +0800, Lu, Baolu wrote: > > On 2020/3/31 14:35, Tian, Kevin wrote: > > >> From: Liu, Yi L > > >> Sent: Sunday, March 22, 2020 8:33 PM > > >> > > >> From: Liu Yi L > > >> > > >> Shared Virtual

Re: [PATCH v1 2/2] vfio/pci: Emulate PASID/PRI capability for VFs

2020-04-07 Thread Raj, Ashok
Hi Alex + Bjorn FWIW I can't understand why PCI SIG went different ways with ATS, where its enumerated on PF and VF. But for PASID and PRI its only in PF. I'm checking with our internal SIG reps to followup on that. On Tue, Apr 07, 2020 at 09:58:01AM -0600, Alex Williamson wrote: > > Is

Re: [PATCH v1 2/2] vfio/pci: Emulate PASID/PRI capability for VFs

2020-04-12 Thread Raj, Ashok
On Wed, Apr 08, 2020 at 10:19:40AM -0600, Alex Williamson wrote: > On Tue, 7 Apr 2020 21:00:21 -0700 > "Raj, Ashok" wrote: > > > Hi Alex > > > > + Bjorn > > + Don > > > FWIW I can't understand why PCI SIG went different ways with ATS,

Re: [PATCH v1 2/2] vfio/pci: Emulate PASID/PRI capability for VFs

2020-04-12 Thread Raj, Ashok
Hi Alex Going through the PCIe Spec, there seems a lot of such capabilities that are different between PF and VF. Some that make sense and some don't. On Sun, Apr 12, 2020 at 08:10:43PM -0700, Raj, Ashok wrote: > > > > > I agree though, I don't know why the SIG would preclu

Re: [PATCH 6/7] x86/traps: Fix up invalid PASID

2020-04-27 Thread Raj, Ashok
Hi Thomas On Sun, Apr 26, 2020 at 05:25:06PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > A #GP fault is generated when ENQCMD instruction is executed without > > a valid PASID value programmed in. > > Programmed in what? > > > The #GP fault handler will initialize the current

Re: [PATCH 6/7] x86/traps: Fix up invalid PASID

2020-04-27 Thread Raj, Ashok
Hi Thomas, On Tue, Apr 28, 2020 at 02:54:59AM +0200, Thomas Gleixner wrote: > Ashok, > > "Raj, Ashok" writes: > > On Sun, Apr 26, 2020 at 05:25:06PM +0200, Thomas Gleixner wrote: > >> Just for the record I also suggested to have a proper errorcode in the &g

Re: [PATCH] iommu: Relax ACS requirement for RCiEP devices.

2020-05-05 Thread Raj, Ashok
Hi Alex + Joerg, accidently missed in the Cc. On Mon, May 04, 2020 at 11:19:36PM -0600, Alex Williamson wrote: > On Mon, 4 May 2020 21:42:16 -0700 > Ashok Raj wrote: > > > PCIe Spec recommends we can relax ACS requirement for RCIEP devices. > > > > PCIe 5.0 Specification. > > 6.12 Access

Re: [PATCH] iommu: Relax ACS requirement for RCiEP devices.

2020-05-05 Thread Raj, Ashok
On Tue, May 05, 2020 at 08:05:14AM -0600, Alex Williamson wrote: > On Mon, 4 May 2020 23:11:07 -0700 > "Raj, Ashok" wrote: > > > Hi Alex > > > > + Joerg, accidently missed in the Cc. > > > > On Mon, May 04, 2020 at 11:19:36PM -0600, Alex Wil

Re: (a design open) RE: [PATCH v1 6/8] vfio/type1: Bind guest page tables to host

2020-05-15 Thread Raj, Ashok
evin > > > -Original Message- > > From: Liu, Yi L > > Sent: Sunday, March 22, 2020 8:32 PM > > To: alex.william...@redhat.com; eric.au...@redhat.com > > Cc: Tian, Kevin ; jacob.jun@linux.intel.com; > > j...@8bytes.org; Raj, Ashok ; Liu, Yi L > >

Re: [PATCH 0/4] PCI, iommu: Factor 'untrusted' check for ATS enablement

2020-05-15 Thread Raj, Ashok
Hi Christoph On Fri, May 15, 2020 at 08:43:51AM -0700, Christoph Hellwig wrote: > Can you please lift the untrusted flag into struct device? It really > isn't a PCI specific concept, and we should not have code poking into > pci_dev all over the iommu code. Just for clarification: All IOMMU's

Re: [PATCH 0/4] PCI, iommu: Factor 'untrusted' check for ATS enablement

2020-05-18 Thread Raj, Ashok
On Mon, May 18, 2020 at 04:47:17PM +0100, David Woodhouse wrote: > On Fri, 2020-05-15 at 10:19 -0700, Raj, Ashok wrote: > > Hi Christoph > > > > On Fri, May 15, 2020 at 08:43:51AM -0700, Christoph Hellwig wrote: > > > Can you please lift the untrusted flag

Re: [PATCH 2/2] iommu/vt-d: Replace intel SVM APIs with generic SVA APIs

2020-03-23 Thread Raj, Ashok
Hi Jean On Fri, Mar 20, 2020 at 10:29:55AM +0100, Jean-Philippe Brucker wrote: > > +#define to_intel_svm_dev(handle) container_of(handle, struct > > intel_svm_dev, sva) > > +struct iommu_sva * > > +intel_svm_bind(struct device *dev, struct mm_struct *mm, void *drvdata) > > +{ > > + struct

Re: [patch V2 00/46] x86, PCI, XEN, genirq ...: Prepare for device MSI

2020-09-03 Thread Raj, Ashok
Hi Thomas, Thanks a ton for jumping in helping on straightening it for IMS!!! On Wed, Aug 26, 2020 at 01:16:28PM +0200, Thomas Gleixner wrote: > This is the second version of providing a base to support device MSI (non > PCI based) and on top of that support for IMS (Interrupt Message Storm)

Re: [PATCH] intel-iommu: don't disable ATS for device without page aligned request

2020-09-10 Thread Raj, Ashok
On Wed, Sep 09, 2020 at 10:17:35PM -0400, Jason Wang wrote: > > > - Original Message - > > Hi Jason > > > > On Wed, Sep 09, 2020 at 04:34:32PM +0800, Jason Wang wrote: > > > Commit 61363c1474b1 ("iommu/vt-d: Enable ATS only if the device uses > > > page aligned address.") disables ATS

Re: [PATCH] intel-iommu: don't disable ATS for device without page aligned request

2020-09-09 Thread Raj, Ashok
Hi Jason On Wed, Sep 09, 2020 at 04:34:32PM +0800, Jason Wang wrote: > Commit 61363c1474b1 ("iommu/vt-d: Enable ATS only if the device uses > page aligned address.") disables ATS for device that can do unaligned > page request. Did you take a look at the PCI specification? Page Aligned Request

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Raj, Ashok
On Tue, Sep 15, 2020 at 08:33:41AM -0300, Jason Gunthorpe wrote: > On Mon, Sep 14, 2020 at 03:44:38PM -0700, Raj, Ashok wrote: > > Hi Jason, > > > > I thought we discussed this at LPC, but still seems to be going in > > circles :-(. > > We discused mdev at L

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-15 Thread Raj, Ashok
On Tue, Sep 15, 2020 at 03:45:10PM -0300, Jason Gunthorpe wrote: > On Tue, Sep 15, 2020 at 11:11:54AM -0700, Raj, Ashok wrote: > > > PASID applies widely to many device and needs to be introduced with a > > > wide community agreement so all scenarios will be supportable. &

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-14 Thread Raj, Ashok
Hi Jason, On Mon, Sep 14, 2020 at 10:47:38AM -0300, Jason Gunthorpe wrote: > On Mon, Sep 14, 2020 at 03:31:13PM +0200, Jean-Philippe Brucker wrote: > > > > Jason suggest something like /dev/sva. There will be a lot of other > > > subsystems that could benefit from this (e.g vDPA). > > > > Do

Re: [PATCH v7 00/16] vfio: expose virtual Shared Virtual Addressing to VMs

2020-09-14 Thread Raj, Ashok
Hi Jason, I thought we discussed this at LPC, but still seems to be going in circles :-(. On Mon, Sep 14, 2020 at 04:00:57PM -0300, Jason Gunthorpe wrote: > On Mon, Sep 14, 2020 at 12:23:28PM -0600, Alex Williamson wrote: > > On Mon, 14 Sep 2020 14:41:21 -0300 > > Jason Gunthorpe wrote: > > >

Re: [RFC PATCH 0/2] iommu: Avoid unnecessary PRI queue flushes

2020-10-15 Thread Raj, Ashok
Hi Jean + Baolu who is looking into this. On Thu, Oct 15, 2020 at 11:00:27AM +0200, Jean-Philippe Brucker wrote: > Add a parameter to iommu_sva_unbind_device() that tells the IOMMU driver > whether the PRI queue needs flushing. When looking at the PCIe spec > again I noticed that most of the

Re: [RFC PATCH 0/2] iommu: Avoid unnecessary PRI queue flushes

2020-10-17 Thread Raj, Ashok
Hi Jean On Fri, Oct 16, 2020 at 09:59:23AM +0200, Jean-Philippe Brucker wrote: > On Thu, Oct 15, 2020 at 11:22:11AM -0700, Raj, Ashok wrote: > > Hi Jean > > > > + Baolu who is looking into this. > > > > > > On Thu, Oct 15, 2020 at 11:00:27AM +0200,

Re: [RFC PATCH 0/2] iommu: Avoid unnecessary PRI queue flushes

2020-10-19 Thread Raj, Ashok
Hi Jean On Mon, Oct 19, 2020 at 04:08:24PM +0200, Jean-Philippe Brucker wrote: > On Sat, Oct 17, 2020 at 04:25:25AM -0700, Raj, Ashok wrote: > > > For devices that *don't* use a stop marker, the PCIe spec says (10.4.1.2): > > > > > > To stop [using a PASID] witho

Re: [bugzilla-dae...@bugzilla.kernel.org: [Bug 209149] New: "iommu/vt-d: Enable PCI ACS for platform opt in hint" makes NVMe config space not accessible after S3]

2020-09-23 Thread Raj, Ashok
Hi Bjorn On Wed, Sep 23, 2020 at 11:03:27AM -0500, Bjorn Helgaas wrote: > [+cc IOMMU and NVMe folks] > > Sorry, I forgot to forward this to linux-pci when it was first > reported. > > Apparently this happens with v5.9-rc3, and may be related to > 50310600ebda ("iommu/vt-d: Enable PCI ACS for

Re: [bugzilla-dae...@bugzilla.kernel.org: [Bug 209149] New: "iommu/vt-d: Enable PCI ACS for platform opt in hint" makes NVMe config space not accessible after S3]

2020-09-24 Thread Raj, Ashok
Hi Alex > > Apparently it also requires to disable RR, and I'm not able to confirm if > > CML requires that as well. > > > > pci_quirk_disable_intel_spt_pch_acs_redir() also seems to consult the same > > table, so i'm not sure why we need the other patch in bugzilla is required. > > If we're

Re: [bugzilla-dae...@bugzilla.kernel.org: [Bug 209149] New: "iommu/vt-d: Enable PCI ACS for platform opt in hint" makes NVMe config space not accessible after S3]

2020-09-24 Thread Raj, Ashok
On Wed, Sep 23, 2020 at 12:45:11PM -0700, Rajat Jain wrote: > On Wed, Sep 23, 2020 at 9:19 AM Raj, Ashok wrote: > > > > Hi Bjorn > > > > > > On Wed, Sep 23, 2020 at 11:03:27AM -0500, Bjorn Helgaas wrote: > > > [+cc IOMMU and NVMe folks] > > >

Re: [bugzilla-dae...@bugzilla.kernel.org: [Bug 209149] New: "iommu/vt-d: Enable PCI ACS for platform opt in hint" makes NVMe config space not accessible after S3]

2020-09-24 Thread Raj, Ashok
Hi Kai + Alex, since he had some of the early quirks authored. On Thu, Sep 24, 2020 at 12:31:53AM +0800, Kai-Heng Feng wrote: > [+Cc Christoph] > > > On Sep 24, 2020, at 00:03, Bjorn Helgaas wrote: > > > > [+cc IOMMU and NVMe folks] > > > > Sorry, I forgot to forward this to linux-pci when

Re: [PATCH V7 0/3] iommu: Add support to change default domain of an iommu group

2020-09-25 Thread Raj, Ashok
Hi Joerg, thanks! On Fri, Sep 25, 2020 at 09:34:23AM +0200, Joerg Roedel wrote: > Hi Ashok, > > On Thu, Sep 24, 2020 at 10:21:48AM -0700, Raj, Ashok wrote: > > Just trying to followup on this series. > > > > Sai has moved out of Intel, hence I'm trying to followup

Re: [Patch V8 0/3] iommu: Add support to change default domain of an iommu group

2020-10-01 Thread Raj, Ashok
Hi Joerg On Thu, Oct 01, 2020 at 02:58:41PM +0200, Joerg Roedel wrote: > Hi Ashok, > > On Fri, Sep 25, 2020 at 12:06:17PM -0700, Ashok Raj wrote: > > Sai Praneeth Prakhya (3): > > iommu: Add support to change default domain of an iommu group > > iommu: Take lock before reading iommu group

Re: [PATCH V7 0/3] iommu: Add support to change default domain of an iommu group

2020-09-28 Thread Raj, Ashok
Hi Joerg On Fri, Sep 25, 2020 at 09:34:23AM +0200, Joerg Roedel wrote: > Hi Ashok, > > On Thu, Sep 24, 2020 at 10:21:48AM -0700, Raj, Ashok wrote: > > Just trying to followup on this series. > > > > Sai has moved out of Intel, hence I'm trying to followup on his b

Re: [PATCH V7 0/3] iommu: Add support to change default domain of an iommu group

2020-09-24 Thread Raj, Ashok
Hi Joerg, On Mon, Sep 07, 2020 at 08:54:44PM -0700, Prakhya, Sai Praneeth wrote: > Presently, the default domain of an iommu group is allocated during boot time > and it cannot be changed later. So, the device would typically be either in > identity (pass_through) mode or the device would be in

Re: [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing)

2020-09-17 Thread Raj, Ashok
Hi Boris, On Thu, Sep 17, 2020 at 09:53:38AM +0200, Borislav Petkov wrote: > On Tue, Sep 15, 2020 at 09:30:07AM -0700, Fenghua Yu wrote: > > +Background > > +== > > + > > +Shared Virtual Addressing (SVA) allows the processor and device to use the > > +same virtual addresses avoiding the

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