Re: [RFC PATCH 5/7] iommu/arm-smmu-v3: For ACPI based device probing, set relevant options for different SMMUv3 implementations.

Linu, On 11.04.17 20:12:43, linucher...@gmail.com wrote: > From: Linu Cherian > > Enable SKIP_PREFETCH option for HiSilicon SMMUv3 model. > Enable PAGE0_REGS_ONLY and USE_SHARED_IRQS options for > Cavium 99xx SMMUv3 model. > > Signed-off-by: Linu Cherian

Re: [PATCH] iommu/arm-smmu: Report smmu type in dmesg

On 07.03.17 18:41:33, Robin Murphy wrote: > On 07/03/17 14:06, Robert Richter wrote: > > On 06.03.17 18:22:08, Robin Murphy wrote: > >> On 06/03/17 13:58, Robert Richter wrote: > >>> The ARM SMMU detection especially depends from system firmware. For > >>>

Re: [PATCH] iommu/arm-smmu: Report smmu type in dmesg

On 08.03.17 16:25:24, Aleksey Makarov wrote: > >-#define ARM_SMMU_MATCH_DATA(name, ver, imp) \ > >-static struct arm_smmu_match_data name = { .version = ver, .model = imp } > >+#define ARM_SMMU_TYPE(var, ver, imp, _name) \ > >+static struct arm_smmu_type var = { .version = ver, .model = imp,

[PATCH] iommu/arm-smmu: Print message when Cavium erratum 27704 was detected

Firmware is responsible for properly enabling smmu workarounds. Print a message for better diagnostics when Cavium erratum 27704 was detected. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/iommu/arm-smmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iom

[PATCH] iommu/arm-smmu: Report smmu type in dmesg

readability. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/iommu/arm-smmu.c | 61 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index abf6496843a6..5c793b

Re: [PATCH] iommu/arm-smmu: Report smmu type in dmesg

On 06.03.17 18:22:08, Robin Murphy wrote: > On 06/03/17 13:58, Robert Richter wrote: > > The ARM SMMU detection especially depends from system firmware. For > > better diagnostic, log the detected type in dmesg. > > This paragraph especially depends from grammar. I think.

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 15.08.17 16:05:49, Lorenzo Pieralisi wrote: > On Tue, Aug 15, 2017 at 05:02:13PM +0200, Robert Richter wrote: > > Lorenzo, Will, > > > > On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > > > ARM IORT specification(rev. C) has added provision to define proximi

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

Lorenzo, Will, On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > ARM IORT specification(rev. C) has added provision to define proximity > domain in SMMUv3 IORT table. Adding required code to parse Proximity > domain and set numa_node of smmv3 platform devices. > > Add code to parse proximity

Re: [PATCH v4] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 25.07.17 10:32:37, Ganapatrao Kulkarni wrote: > ARM IORT specification(rev. C) has added provision to define proximity > domain in SMMUv3 IORT table. Adding required code to parse Proximity > domain and set numa_node of smmv3 platform devices. > > Add code to parse proximity domain in SMMUv3

Re: [PATCH v3 2/2] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 04.07.17 11:07:59, Lorenzo Pieralisi wrote: > On Wed, Jun 28, 2017 at 07:47:50PM +0200, Robert Richter wrote: > > On 15.06.17 14:46:03, Lorenzo Pieralisi wrote: > > > On Thu, Jun 08, 2017 at 10:14:19AM +0530, Ganapatrao Kulkarni wrote: > > > > Add code to parse p

Re: [Devel] [RESEND PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

On 23.06.17 19:04:36, Geetha sowjanya wrote: > From: Geetha Sowjanya > > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq > lines for gerror, eventq and cmdq-sync. > > New named irq "combined" is set as a errata workaround, which allows

Re: [PATCH v3 2/2] acpi/iort: numa: Add numa node mapping for smmuv3 devices

On 15.06.17 14:46:03, Lorenzo Pieralisi wrote: > On Thu, Jun 08, 2017 at 10:14:19AM +0530, Ganapatrao Kulkarni wrote: > > Add code to parse proximity domain in SMMUv3 IORT table to > > set numa node mapping for smmuv3 devices. > > > > Signed-off-by: Ganapatrao Kulkarni

[PATCH] iommu: Print a message with the default domain type created

to determine if direct mapping is enabled. Print message with the default domain type case. Signed-off-by: Robert Richter <rrich...@cavium.com> --- drivers/iommu/iommu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c

Re: [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

On 27.04.17 17:16:21, Geetha sowjanya wrote: > From: Geetha > > Cavium CN99xx SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines for gerror, eventq

Re: [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds

On 08.05.17 20:45:36, Linu Cherian wrote: > On Sat May 06, 2017 at 12:22:50AM +0200, Robert Richter wrote: > > On 05.05.17 17:38:04, Geetha sowjanya wrote: > > > From: Linu Cherian <linu.cher...@cavium.com> > > > > > > Cavium ThunderX2 SMMUv3 imple

Re: [PATCH 1/2] acpica: iort: Update SMMU models for IORT rev. C

intel.com> > Signed-off-by: Robin Murphy <robin.mur...@arm.com> For the whole series: Acked-by: Robert Richter <rrich...@cavium.com> Tested--by: Robert Richter <rrich...@cavium.com> Thanks Robin ___ iommu mailing list iommu@lis

Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

On 30.05.17 17:33:39, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 implementation doesn't support second page in SMMU > register space. Hence, resource size is set as 64k for this model. > > Signed-off-by: Linu Cherian >

Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

On 20.06.17 10:19:43, Robert Richter wrote: > On 30.05.17 17:33:39, Geetha sowjanya wrote: > > From: Linu Cherian <linu.cher...@cavium.com> > > + /* > > +* Override the size, for Cavium ThunderX2 implementation > > +* which doesn't suppo

Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

arm64 include files and the closest was arch/arm64/include/asm/acpi.h, bug this seems not really suitable to me.) I have created a separate patch to be applied at first below. We can revert it after acpica was updated. -Robert From ad7f0112a2a71059c32bd315835c33cc7bc660b8 Mon Sep 17 00:00:00 200

[PATCH] iommu/arm-smmu-v3, acpi: Add temporary Cavium SMMU-V3 IORT model number definitions

On 23.06.17 06:55:41, Robert Richter wrote: > On 22.06.17 22:04:37, Lorenzo Pieralisi wrote: > > On Thu, Jun 22, 2017 at 09:35:35PM +0200, Robert Richter wrote: > > > On 22.06.17 19:58:22, Will Deacon wrote: > > > > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deaco

Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

On 22.06.17 22:04:37, Lorenzo Pieralisi wrote: > On Thu, Jun 22, 2017 at 09:35:35PM +0200, Robert Richter wrote: > > On 22.06.17 19:58:22, Will Deacon wrote: > > > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote: > > > > On Thu, Jun 22, 2017 at 05:35:35P

Re: [Devel] [RESEND PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

On 27.06.17 20:28:14, Geetha Akula wrote: > On Tue, Jun 27, 2017 at 7:36 PM, Will Deacon <will.dea...@arm.com> wrote: > > On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote: > >> On 23.06.17 19:04:36, Geetha sowjanya wrote: > >> > From: Geetha Sowja

Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C

art updating their firmware tables to use them. > > CC: Rafael J. Wysocki <r...@rjwysocki.net> > CC: Robert Moore <robert.mo...@intel.com> > CC: Lv Zheng <lv.zh...@intel.com> > Acked-by: Robert Richter <rrich...@cavium.com> > Tested-by: Robert Richter <rric

Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C

On 22.05.17 17:49:17, Robert Richter wrote: > On 22.05.17 16:06:37, Robin Murphy wrote: > > IORT revision C has been published with a number of new SMMU > > implementation identifiers. Since IORT doesn't have any way of falling > > back to a more generic model code, we real

Re: [PATCH v3 1/7] iommu/arm-smmu-v3: Introduce SMMU option PAGE0_REGS_ONLY for ThunderX2 errata #74

On 08.05.17 14:47:39, Linu Cherian wrote: > Have pasted here the relevant changes for doing fixups on smmu base instead > of offset to get feedback. To me this looks better than the ARM_SMMU_EVTQ_*() macros. It still needs some more shaping (e.g. maybe remove page1_base var and call

Re: [PATCH v3 1/7] iommu/arm-smmu-v3: Introduce SMMU option PAGE0_REGS_ONLY for ThunderX2 errata #74

On 08.05.17 10:59:46, Robin Murphy wrote: > On 08/05/17 10:17, Linu Cherian wrote: > > This actually results in more lines of changes. If you think the below > > approach is still better, will post a V4 of this series with this change. > > Why not just do this?: > > static inline unsigned long

Re: [PATCH v3 2/7] iommu/arm-smmu-v3: Do resource size checks based on SMMU

On 08.05.17 15:14:37, Linu Cherian wrote: > On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote: > > On 05.05.17 17:38:06, Geetha sowjanya wrote: > > > From: Linu Cherian <linu.cher...@cavium.com> > > > > > > With implementations supporting

Re: [PATCH v3 2/7] iommu/arm-smmu-v3: Do resource size checks based on SMMU

On 08.05.17 16:20:49, Linu Cherian wrote: > > On Mon May 08, 2017 at 12:09:32PM +0200, Robert Richter wrote: > > On 08.05.17 15:14:37, Linu Cherian wrote: > > > On Sat May 06, 2017 at 12:18:44AM +0200, Robert Richter wrote: > > > > On 05.05.17 17:38:06, Geetha sow

Re: [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds

On 05.05.17 17:38:04, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines and

Re: [PATCH v3 5/7] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model

On 05.05.17 17:38:09, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 implementation doesn't support second page in SMMU > register space. Hence, resource size is set as 64k for this model. > > Signed-off-by: Linu Cherian >

Re: [PATCH v3 1/7] iommu/arm-smmu-v3: Introduce SMMU option PAGE0_REGS_ONLY for ThunderX2 errata #74

On 05.05.17 17:38:05, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option will be enabled as an errata workaround. > > This option when turned on, replaces all page 1

Re: [PATCH v3 1/7] iommu/arm-smmu-v3: Introduce SMMU option PAGE0_REGS_ONLY for ThunderX2 errata #74

On 05.05.17 17:38:05, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option will be enabled as an errata workaround. > > This option when turned on, replaces all page 1

Re: [PATCH v3 2/7] iommu/arm-smmu-v3: Do resource size checks based on SMMU

On 05.05.17 17:38:06, Geetha sowjanya wrote: > From: Linu Cherian > > With implementations supporting only page 0 register space, > resource size can be 64k as well and hence perform size checks > based on SMMU option PAGE0_REGS_ONLY. > > For this,

[PATCH v2] iommu/iova: Fix tracking of recently failed iova address

On 18.03.19 15:19:23, Robin Murphy wrote: > On 15/03/2019 15:56, Robert Richter wrote: > > We track the smallest size that failed for a 32 bit allocation. The > > Size decreases only and if we actually walked the tree and noticed an > > allocation failure. Current code

[PATCH] iommu/iova: Fix tracking of recently failed iova address size

might go the slow path again even if we have seen a failure before for the same or a smaller size. Cc: # 4.20+ Fixes: bee60e94a1e2 ("iommu/iova: Optimise attempts to allocate iova from 32bit address range") Signed-off-by: Robert Richter --- drivers/iommu/iova.c | 5 +++-- 1 file

Re: [RFC PATCH 05/11] EDAC: Remove Calxeda drivers

On 18.02.20 11:13:15, Rob Herring wrote: > Cc: Borislav Petkov > Cc: Mauro Carvalho Chehab > Cc: Tony Luck > Cc: James Morse > Cc: Robert Richter > Cc: linux-e...@vger.kernel.org > Signed-off-by: Rob Herring > --- > Do not apply yet. > > MAINTAINERS