[siemens/jailhouse] fa6569: arm64: Dispatch ICC_SGI1R accesses

Branch: refs/heads/next Home: https://github.com/siemens/jailhouse Commit: fa656998e5f49014e03a5e82be65d9bd27f609a2 https://github.com/siemens/jailhouse/commit/fa656998e5f49014e03a5e82be65d9bd27f609a2 Author: Jan Kiszka Date: 2017-09-14 (Thu, 14 Sep

Re: [PATCH] x86,mmio: Add support for 3 more instructions on the MMIO dispatcher

* Jan Kiszka [2017-09-14 19:52:21 +]: > On 2017-09-14 19:05, Gustavo Lima Chaves wrote: > >>> break; > >>> } else if (op[2].modrm.rm != 4) { /* no SIB */ > >>> break; > >>> @@ -168,6 +191,16 @@ restart: > >>> else > >>>

Re: [PATCH] x86,mmio: Add support for 3 more instructions on the MMIO dispatcher

On 2017-09-14 19:05, Gustavo Lima Chaves wrote: >>> break; >>> } else if (op[2].modrm.rm != 4) { /* no SIB */ >>> break; >>> @@ -168,6 +191,16 @@ restart: >>> else >>> inst.reg_num = 15 - op[2].modrm.reg; >>> >>> +final: >>> +

Re: [PATCH] x86,mmio: Add support for 3 more instructions on the MMIO dispatcher

* Jan Kiszka [2017-09-14 06:42:38 +]: > On 2017-09-14 01:37, Gustavo Lima Chaves wrote: > > Those are: > > > > X86_OP_MOV_IMMEDIATE_TO_MEM 0xc7 > > X86_OP_MOV_MEM_TO_RAX 0xa1 > > X86_OP_MOV_RAX_TO_MEM

Re: [PATCH v2 0/3] arm: Add arch specific sysreg definitions

On 2017-09-14 17:02, Lokesh Vutla wrote: > Hi Jan, > > On 9/14/2017 7:39 PM, Jan Kiszka wrote: >> On 2017-09-14 16:03, Jan Kiszka wrote: >>> On 2017-09-14 10:35, Lokesh Vutla wrote: From: Lokesh Vutla arm: Add arch specific sysreg definitions Changes

Re: [PATCH v2 0/3] arm: Add arch specific sysreg definitions

Hi Jan, On 9/14/2017 7:39 PM, Jan Kiszka wrote: > On 2017-09-14 16:03, Jan Kiszka wrote: >> On 2017-09-14 10:35, Lokesh Vutla wrote: >>> From: Lokesh Vutla >>> >>> arm: Add arch specific sysreg definitions >>> >>> Changes since v1: >>> - Fixed build error with ARM. >>> >>>

[siemens/jailhouse] 5cef75: core, configs: Add GIC version to ARM platform inf...

Branch: refs/heads/next Home: https://github.com/siemens/jailhouse Commit: 5cef75c3f712ab6e49314772851f10c4c2341305 https://github.com/siemens/jailhouse/commit/5cef75c3f712ab6e49314772851f10c4c2341305 Author: Jan Kiszka Date: 2017-09-14 (Thu, 14 Sep

Re: [PATCH v2 0/3] arm: Add arch specific sysreg definitions

On 2017-09-14 16:03, Jan Kiszka wrote: > On 2017-09-14 10:35, Lokesh Vutla wrote: >> From: Lokesh Vutla >> >> arm: Add arch specific sysreg definitions >> >> Changes since v1: >> - Fixed build error with ARM. >> >> Lokesh Vutla (2): >> arm: gicv3: Add arch specific List

Re: [PATCH v2 0/3] arm: Add arch specific sysreg definitions

On 2017-09-14 10:35, Lokesh Vutla wrote: > From: Lokesh Vutla > > arm: Add arch specific sysreg definitions > > Changes since v1: > - Fixed build error with ARM. > > Lokesh Vutla (2): > arm: gicv3: Add arch specific List registers acccesses > arm: gicv3: Add arch

Re: [PATCH v2 03/16] arm: provide correct caller CPU ID when reinjecting SGIs

On 2017-09-14 15:09, Ralf Ramsauer wrote: > Hi Jan, > > I just accidentally came across commit 05c1d67e0a79 ("arm: Remove cpuid > from pending_irq") from last year. > > Seems like there already has been a preparation for the feature I'm now > reintroducing. Can you remember why you removed the

Re: [PATCH v2 03/16] arm: provide correct caller CPU ID when reinjecting SGIs

Hi Jan, I just accidentally came across commit 05c1d67e0a79 ("arm: Remove cpuid from pending_irq") from last year. Seems like there already has been a preparation for the feature I'm now reintroducing. Can you remember why you removed the code instead of providing the correct CPU ID? Ralf On

Re: [PATCH 2/3] arm: gicv3: Add arch specific List registers acccesses

On Thursday 14 September 2017 01:29 PM, Jan Kiszka wrote: > On 2017-09-12 14:05, Lokesh Vutla wrote: >> From: Lokesh Vutla >> >> With system register access enabled, gicv3 List registers >> can be accessed in the following manner: >> AArch64: ICH_LR_EL2 >> AArch32: ICH_LR,

Re: [PATCH 2/3] arm: gicv3: Add arch specific List registers acccesses

On Thursday 14 September 2017 01:29 PM, Jan Kiszka wrote: > On 2017-09-12 14:05, Lokesh Vutla wrote: >> From: Lokesh Vutla >> >> With system register access enabled, gicv3 List registers >> can be accessed in the following manner: >> AArch64: ICH_LR_EL2 >> AArch32: ICH_LR,

Re: [RFC] Device-Tree for cell configuration

Am Wed, 13 Sep 2017 15:59:57 +0200 schrieb Ralf Ramsauer : > Hi Lokesh, > > thanks for picking up this topic -- we already had some offline > discussions on that before. > > On 09/13/2017 10:49 AM, Jan Kiszka wrote: > > Hi Lokesh > > > > On 2017-09-12 16:03,

Re: [PATCH] x86,mmio: Add support for 3 more instructions on the MMIO

Am Wed, 13 Sep 2017 16:37:49 -0700 schrieb Gustavo Lima Chaves : > This makes Zephyr payloads doing pristine xAPIC-mode access to LOAPIC > registers work out-of-the-box. Since it's small and simple enough, I > guess it won't hurt to have it. The patches for the

Re: [PATCH 2/3] arm: gicv3: Add arch specific List registers acccesses

On 2017-09-12 14:05, Lokesh Vutla wrote: > From: Lokesh Vutla > > With system register access enabled, gicv3 List registers > can be accessed in the following manner: > AArch64: ICH_LR_EL2 > AArch32: ICH_LR, ICH_LRC > Adding support for reading these registers accordingly. >

[PATCH v2 16/17] inmates: arm-common: Select GIC version from mach header

From: Jan Kiszka Select the GIC implementation of the inmate lib based on the GIC_VERSION is defined. This allows to compile both GIC v2 and - on ARM - v3 in by default and let the linker sort out what is unused, simplify the configuration of the available boards.

[PATCH v2 13/17] core, configs: Add GIC version to ARM platform info of system config

From: Jan Kiszka In preparation of selecting the GIC version via the config, add a version field to platform_info.arm and set it for all ARM configs. Signed-off-by: Jan Kiszka --- Changes in v2: - update header revision configs/amd-seattle.c

Re: [PATCH] x86,mmio: Add support for 3 more instructions on the MMIO dispatcher

On 2017-09-14 01:37, Gustavo Lima Chaves wrote: > Those are: > > X86_OP_MOV_IMMEDIATE_TO_MEM 0xc7 > X86_OP_MOV_MEM_TO_RAX 0xa1 > X86_OP_MOV_RAX_TO_MEM 0xa3 Let's call this AX_TO_MEM / MEM_TO_AX - the register width depends on

Re: [PATCH] core, vmx: New MSR bitmap format, now a whitelist

On 2017-09-14 01:43, Gustavo Lima Chaves wrote: > On Thursday, August 31, 2017 at 2:17:02 PM UTC-7, Gustavo Lima Chaves wrote: >> This is a first take on the TODO-list entry >> >> - whitelist-based MSR access [v1.0] >> >> *for Intel architecture*. All the architectural MSRs where given a look >>

Re: [PATCH 1/1] tools: config-create: Use correct length for AER capability

On 2017-09-14 02:28, Gustavo Lima Chaves wrote: > * Jan Kiszka [2017-08-31 13:24:20 +]: > >> On 2017-08-31 02:15, Otavio Pontes wrote: >>> Use length defined by PCI specification for AER (Advanced Error >>> Reporting) capability. This is relevant if PCI device is