Re: [PATCH] README: drop the warning

On 29/06/20 12:54 pm, peng@nxp.com wrote: > From: Peng Fan > > Jailhouse has been chosen by Semiconductor Companies(TI, NXP) > in regular software releases. And it has also been deployed > in real products. > > So let's mark jailhouse product ready, drop the warning that > make people

Re: [PATCH 0/2] boot jailhouse before root cell linux

On 05/03/20 3:09 PM, peng@nxp.com wrote: > From: Peng Fan > > This patchset tested on i.MX8MN arm64 with quad A53 cores > > Patch 1 is to align jailhouse_system. Since the loader not have > MMU enabled, unaligned access will cause abort. > > Patch 2 is not that well orgnized. It does

Re: [PATCH v4 4/4] configs: arm64: Add Linux demo for j721-evm board

On 24/12/19 3:18 PM, Nikhil Devshatwar wrote: > > > On 24/12/19 9:42 am, Lokesh Vutla wrote: >> On 23/12/19 8:43 PM, Nikhil Devshatwar wrote: >>> Add the linux demo cell config for j721e-evm board. >>> Also add the required device tree for booting Linux kernel >>> in the inmate cell. >>> >>>

Re: [PATCH v4 4/4] configs: arm64: Add Linux demo for j721-evm board

On 23/12/19 8:43 PM, Nikhil Devshatwar wrote: > Add the linux demo cell config for j721e-evm board. > Also add the required device tree for booting Linux kernel > in the inmate cell. > > This cell config acts as a reference for partitioning > devices across the 2 Linux cells. > This will be

Re: [PATCH 0/8] Add cache coloring support for Arm

On 02/12/19 1:03 PM, Jan Kiszka wrote: > On 02.12.19 08:24, Peng Fan wrote: >> Hi Jan, >> >>> -Original Message- >>> From: jailhouse-dev@googlegroups.com >>> On Behalf Of Jan Kiszka >>> Sent: 2019年12月2日 14:27 >>> To: Peng Fan ; Marco Solieri ; Jailhouse >>> >>> Cc:

Re: kernel build failure

On 24/10/19 4:28 PM, Jan Kiszka wrote: > On 24.10.19 12:09, Peng Fan wrote: >>> Subject: Re: kernel build failure >>> >>> On 24.10.19 08:07, 'Lokesh Vutla' via Jailhouse wrote: >>>> >>>> >>>> On 23/10/19 3:47 PM, Peng Fan wro

Re: kernel build failure

On 23/10/19 3:47 PM, Peng Fan wrote: > Hi Jan, > > When MODVERSIONS and ASM_MODVERSIONS defined, your queue/jailhouse tree will > have build failure for ARM64. > > MODPOST vmlinux.o > WARNING: EXPORT symbol "__hyp_stub_vectors" [vmlinux] version generation > failed, symbol will not be

[PATCH] tools: cell-linux: arm: Do not page align the ramdisk size

When updating linux initrd size in inmate DT, the size is aligned to page. Because of this some initrd images were not able to mount by inmate as Linux is seeing junk at end of specified initrd. Pass the exact initrd size to the Linux kernel. Signed-off-by: Lokesh Vutla ---

Re: [PATCH v3 4/4] configs: arm64: Add Linux demo for j721-evm board

On 04/09/19 5:52 PM, Nikhil Devshatwar wrote: > Add the linux demo cell config for j721e-evm board. > Also add the required device tree for booting Linux kernel > in the inmate cell. > > This cell config acts as a reference for partitioning > devices across the 2 Linux cells. > This will be

Re: [PATCH v3 2/4] configs: arm64: Add support for k3-j721-evm board

On 04/09/19 5:52 PM, Nikhil Devshatwar wrote: > k3-j721e-evm is the new evaluation module from Texas Instruments > which has the j721e SoC. (aka DRA829) It has a dual core > ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports, > 6x UART ports, 5x ethernet ports, SD and eMMC interfaces for >

Re: IO access in jailhouse root cell

On 30/08/19 4:50 PM, Jan Kiszka wrote: > On 30.08.19 13:10, Lokesh Vutla wrote: >> Hi Jan, >> >> On 30/08/19 11:51 AM, Jan Kiszka wrote: >>> On 30.08.19 07:38, Lokesh Vutla wrote: On 29/08/19 8:21 PM, Jan Kiszka wrote: > On 29.08.19 16:10, Oliver Schwartz wrote: >> >>

Re: IO access in jailhouse root cell

On 29/08/19 8:21 PM, Jan Kiszka wrote: > On 29.08.19 16:10, Oliver Schwartz wrote: >> >> >>> On 29 Aug 2019, at 15:14, Jan Kiszka wrote: >>> >>> On 29.08.19 15:06, Oliver Schwartz wrote: > On 29 Aug 2019, at 10:08, Jan Kiszka wrote: > > On 29.08.19 08:41, Oliver Schwartz wrote:

Re: [PATCH v4 2/6] arm-common: Introduce iommu functionality

Hi Jan, [..snip..] >> >>   void __attribute__((noreturn)) arch_panic_stop(void) >> diff --git a/hypervisor/arch/arm-common/include/asm/iommu.h >> b/hypervisor/arch/arm-common/include/asm/iommu.h >> new file mode 100644 >> index ..67ac34eb >> --- /dev/null >> +++

Re: [PATCH v2 4/4] configs: arm64: Add Linux demo for j721-evm board

On 19/08/19 10:29 PM, Jan Kiszka wrote: > On 19.08.19 18:50, Lokesh Vutla wrote: >> >> >> On 19/08/19 7:56 PM, Nikhil Devshatwar wrote: >>> Add the linux demo cell config for j721e-evm board. >>> Also add the required device tree for booting Linux kernel >>> in the inmate cell. >>> >>> This

Re: [PATCH v2 2/4] configs: arm64: Add support for k3-j721-evm board

On 19/08/19 7:56 PM, Nikhil Devshatwar wrote: > k3-j721e-evm is the new evaluation module from Texas Instruments > which has the j721e SoC. (aka DRA829) It has a dual core > ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports, > 6x UART ports, 5x ethernet ports, SD and eMMC interfaces for >

Re: [PATCH v2 4/4] configs: arm64: Add Linux demo for j721-evm board

On 19/08/19 7:56 PM, Nikhil Devshatwar wrote: > Add the linux demo cell config for j721e-evm board. > Also add the required device tree for booting Linux kernel > in the inmate cell. > > This cell config acts as a reference for partitioning > devices across the 2 Linux cells. > This will be

Re: [PATCH v5 0/6] arm64: iommu: Add support for SMMUv3 stage 1 and 2 translations

On 11/08/19 11:03 PM, Jan Kiszka wrote: > On 07.08.19 09:55, 'Lokesh Vutla' via Jailhouse wrote: >> This series adds support for SMMUv3. Stream IDs have been added to the >> cell config and they need to be specified in the config before a cell >> can use a stream. >>

[PATCH v5 5/6] arm64: iommu: smmu-v3: Add data structure initialization and stage 2 for SMMUv3

From: Pratyush Yadav A System Memory Management Unit(SMMU) performs a task analogous to a CPU's MMU, translating addresses for device requests from system I/O devices before the requests are passed into the system interconnect. Implement a driver for SMMU v3 that maps and unmaps memory for

[PATCH v5 3/6] core: Add stream id list in the cell config

From: Nikhil Devshatwar When ARM IOMMU drivers are supported, it will setup the IO address translation tables unique for each DMA context in the system. A typical DMA context is identified by an integer called stream id. To setup the correct IOMMU mapping, hypervisor should know list of all the

[PATCH v5 4/6] arm64: iommu: smmu-v3: Add support for smmu v3 configuration from config files

Add SMMU v3 type to jailhouse_iommu_type. Signed-off-by: Lokesh Vutla Signed-off-by: Jan Kiszka --- include/jailhouse/cell-config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/jailhouse/cell-config.h b/include/jailhouse/cell-config.h index d43800fb..d435b9f7 100644 ---

[PATCH v5 6/6] arm64: iommu: smmu-v3: Add support for stage 1 translations

From: Pratyush Yadav An emulated SMMU is presented to inmates by trapping access to the MMIO registers to enable stage 1 translations. Accesses to the SMMU memory mapped registers are trapped and then routed to the emulated SMMU. This is not emulation in the sense that we fully emulate the

[PATCH v5 2/6] arm-common: Introduce iommu functionality

From: Nikhil Devshatwar Add the iommu hooks for ARM and ARM64 architectures with dummy implementations and update the Kbuild to include new iommu files Introduce following hooks: iommu_map_memory - Setup iommu mapping for the memory region iommu_unmap_memory - Unmap the iommu mapping for the

[PATCH v5 1/6] iommu: x86: Generalize iommu definition

From: Nikhil Devshatwar Right now, jailhouse only supports iommu for x86. Generalize the data structures to support iommus of different types Assumption is that each jailhouse_system can define iommu instances of different types. Extend the jailhouse_iommu to add type info. Update the x86

[PATCH v5 0/6] arm64: iommu: Add support for SMMUv3 stage 1 and 2 translations

This series adds support for SMMUv3. Stream IDs have been added to the cell config and they need to be specified in the config before a cell can use a stream. The SMMU driver exposes an emulated SMMU to the guests cells by trapping access to the MMIO registers. This is not emulation in the sense

Re: [PATCH v3 1/6] iommu: x86: Generalize iommu definition

Hi Jan, On 05/08/19 7:15 PM, Jan Kiszka wrote: > On 05.08.19 15:25, Ralf Ramsauer wrote: >> Hi, >> >> On 7/9/19 3:48 PM, 'Pratyush Yadav' via Jailhouse wrote: >>> From: Nikhil Devshatwar >>> >>> Right now, jailhouse only supports iommu for x86. >>> Generalize the data structures to support

Re: [PATCH v4 5/6] arm64: iommu: smmu-v3: Add data structure initialization and stage 2 for SMMUv3

Hi Jan, [..snip..] > +static int arm_smmuv3_cell_init(struct cell *cell) > +{ > + struct jailhouse_iommu *iommu; > + struct arm_smmu_cmdq_ent cmd; > + int ret, i, j, sid; > + > + if (!iommu_count_units()) > + return 0; > + > + iommu =

[PATCH v4 4/6] arm64: iommu: smmu-v3: Add support for smmu v3 configuration from config files

Add SMMU v3 type to jailhouse_iommu_type. Signed-off-by: Lokesh Vutla --- include/jailhouse/cell-config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/jailhouse/cell-config.h b/include/jailhouse/cell-config.h index 73dc8ca1..b2eae054 100644 --- a/include/jailhouse/cell-config.h

[PATCH v4 5/6] arm64: iommu: smmu-v3: Add data structure initialization and stage 2 for SMMUv3

From: Pratyush Yadav A System Memory Management Unit(SMMU) performs a task analogous to a CPU's MMU, translating addresses for device requests from system I/O devices before the requests are passed into the system interconnect. Implement a driver for SMMU v3 that maps and unmaps memory for

[PATCH v4 6/6] arm64: iommu: smmu-v3: Add support for stage 1 translations

From: Pratyush Yadav An emulated SMMU is presented to inmates by trapping access to the MMIO registers to enable stage 1 translations. Accesses to the SMMU memory mapped registers are trapped and then routed to the emulated SMMU. This is not emulation in the sense that we fully emulate the

[PATCH v4 3/6] core: Add stream id list in the cell config

From: Nikhil Devshatwar When ARM IOMMU drivers are supported, it will setup the IO address translation tables unique for each DMA context in the system. A typical DMA context is identified by an integer called stream id. To setup the correct IOMMU mapping, hypervisor should know list of all the

[PATCH v4 2/6] arm-common: Introduce iommu functionality

From: Nikhil Devshatwar Add the iommu hooks for ARM and ARM64 architectures with dummy implementations and update the Kbuild to include new iommu files Introduce following hooks: iommu_map_memory - Setup iommu mapping for the memory region iommu_unmap_memory - Unmap the iommu mapping for the

[PATCH v4 1/6] iommu: x86: Generalize iommu definition

From: Nikhil Devshatwar Right now, jailhouse only supports iommu for x86. Generalize the data structures to support iommus of different types Assumption is that each jailhouse_system can define iommu instances of different types. Extend the jailhouse_iommu to add type info. Update the x86

[PATCH v4 0/6] arm64: iommu: Add support for SMMUv3 stage 1 and 2 translations

This series adds support for SMMUv3. Stream IDs have been added to the cell config and they need to be specified in the config before a cell can use a stream. The SMMU driver exposes an emulated SMMU to the guests cells by trapping access to the MMIO registers. This is not emulation in the sense

Re: [PATCH v3 1/6] iommu: x86: Generalize iommu definition

On 16/07/19 9:44 AM, Jan Kiszka wrote: > On 09.07.19 15:48, 'Pratyush Yadav' via Jailhouse wrote: >> From: Nikhil Devshatwar >> >> Right now, jailhouse only supports iommu for x86. >> Generalize the data structures to support iommus of different types >> >> Assumption is that each

Re: [PATCH v3 5/6] arm64: iommu: smmu-v3: Add data structure initialization and stage 2 for SMMUv3

On 19/07/19 11:53 AM, Jan Kiszka wrote: > On 09.07.19 22:48, 'Pratyush Yadav' via Jailhouse wrote: >> A System Memory Management Unit(SMMU) performs a task analogous to a >> CPU's MMU, translating addresses for device requests from system I/O >> devices before the requests are passed into the

Re: [PATCH v3 2/6] arm-common: Introduce iommu functionality

On 16/07/19 10:06 AM, Jan Kiszka wrote: > On 09.07.19 15:48, 'Pratyush Yadav' via Jailhouse wrote: >> From: Nikhil Devshatwar >> >> Add the iommu hooks for ARM and ARM64 architectures with >> dummy implementations. >> Update the Kbuild to include new iommu files >> >> Introduce following

[PATCH v2 2/4] configs: inmates: k3-am654: Add gic and uart demo configurations

Add UART and GIC based demos for AM654 IDK. Signed-off-by: Lokesh Vutla Signed-off-by: Nikhil Devshatwar --- configs/arm64/k3-am654-gic-demo.c | 74 ++ configs/arm64/k3-am654-uart-demo.c | 74 ++ 2 files changed, 148 insertions(+)

[PATCH v2 3/4] configs: inmates: k3-am654: Add linux inmate demo configuration

Add an inmate configuration file for running Linux as an inmate on AM654 IDK. Signed-off-by: Lokesh Vutla --- configs/arm64/k3-am654-idk-linux-demo.c | 153 1 file changed, 153 insertions(+) create mode 100644 configs/arm64/k3-am654-idk-linux-demo.c diff --git

[PATCH v2 0/4] Add support for AM654 idk

The AM654 SoC is a lead device of the TI's K3 Multicore SoC architecture platform, targeted for broad market and industrial control with aim to meet the complex processing needs of modern embedded products. This series add support for the AM654 based idk to Jailhouse. Kernel used:

[PATCH v2 1/4] configs: k3-am654: Add root cell configuration

Add root cell configuration for TI's AM654 based idk. Linux root cell DTS should reserve the following memory: reg = <0x8 0xdfb0 0x0 0x2050>; Signed-off-by: Lokesh Vutla --- configs/arm64/k3-am654-idk.c | 227 +++ 1 file changed, 227 insertions(+)

[PATCH v2 4/4] configs: k3-am654: Add linux inmate demo dts

Add a demo device tree running Linux as an inmate on AM654 IDK. Linux is assigned with 256MB RAM, 1 serial port(MCU UART0) and ability to communicate with system firmware. Signed-off-by: Lokesh Vutla --- configs/arm64/dts/inmate-k3-am654-idk.dts | 164 ++ 1 file changed, 164

Re: [PATCH 1/4] configs: k3-am654: Add root cell configuration

On 24/03/19 4:14 PM, Jan Kiszka wrote: > On 20.03.19 13:47, 'Lokesh' via Jailhouse wrote: >> From: Lokesh Vutla >> >> Add root cell configuration for TI's AM654 based platform. > > Is the configuration here common for every board that embeds the am654? Or > does > it also contain EVM-specific

Re: [RFC PATCH 2/5] arm-common: Introduce iommu functionality

On 22/03/19 10:53 PM, Jan Kiszka wrote: > On 22.03.19 10:44, Lokesh wrote: >> From: Nikhil Devshatwar >> >> Add the iommu hooks for ARM and ARM64 architectures with >> dummy implementations. >> Update the Kbuild to include new iommu files >> >> Introduce following hooks: >> iommu_map_memory -

Re: [RFC PATCH 1/5] iommu: x86: Generalize iommu definition

On 3/22/2019 5:15 PM, Jan Kiszka wrote: > On 22.03.19 10:44, 'Lokesh' via Jailhouse wrote: >> From: Nikhil Devshatwar >> >> Right now, jailhouse only suppports iommu for x86. >> Generalize the data structures to support iommus of different types >> >> Assumption is that each jailhouse_system

Re: [RFC PATCH 3/5] core: Add stream id list in the VMconfig

On 3/22/2019 5:33 PM, Jan Kiszka wrote: > On 22.03.19 10:44, 'Lokesh' via Jailhouse wrote: >> From: Nikhil Devshatwar >> >> When IOMMU drivers are supported, it will setup the IO address >> translation tables unique for each DMA context in the system. >> >> A typical DMA context is identified

Re: [PATCH 0/4] Add support for AM654 evm

On 20/03/19 7:54 PM, Jan Kiszka wrote: > On 20.03.19 15:19, Lokesh Vutla wrote: >> Hi Jan, >> >> On 20/03/19 7:24 PM, Jan Kiszka wrote: >>> On 20.03.19 13:47, Lokesh wrote: From: Lokesh Vutla The AM654 SoC is a lead device of the TI's K3 Multicore SoC architecture platform,

Re: Jailhouse on iMX8M

On 10/01/19 11:08 AM, Peng Fan wrote: > Hi Lokesh > >> -Original Message- >> From: 'Lokesh Vutla' via Jailhouse [mailto:jailhouse-dev@googlegroups.com] >> Sent: 2019年1月8日 21:24 >> To: Peng Fan >> Cc: jailhouse-dev@googlegroups.com >> Sub

Re: Jailhouse on iMX8M

Hi Peng, Sorry to bring up an old thread. On 13/03/18 9:43 AM, Peng Fan wrote: > Hi Anders, > On Mon, Mar 12, 2018 at 04:52:35PM +0100, Anders T??rnqvist wrote: >> I noticed that there are development ongoing for a iMX8M based board. Great! >> >> When reading in the reference manual for

[PATCH v2] arm-common: gic-v3: Mark last CPUs GICR as last

From: Lokesh Vutla There are scenarios where Linux boots up with less number of cores than the SoC supports. In such cases, finding GICR region marked with GICR_TYPER_Last is not possible for any non-root cell. This is because hypervisor gives an unhandled trap to any access

Re: [PATCH 2/2] arm-common: gic-v3: Mark last CPUs GICR as last

On 3/17/2018 9:11 PM, Jan Kiszka wrote: > On 2018-03-15 13:58, Lokesh Vutla wrote: >> >> >> On Thursday 15 March 2018 06:17 PM, Jan Kiszka wrote: >>> On 2018-03-15 00:17, Lokesh Vutla wrote: On Thursday 15 March 2018 01:02 AM, Jan Kiszka wrote: > On 2018-03-14 05:54, Lokesh

Re: [PATCH 1/2] core: Introduce an api to find last cpu

On Thursday 15 March 2018 06:16 PM, Jan Kiszka wrote: > On 2018-03-15 00:20, Lokesh Vutla wrote: >> >> >> On Thursday 15 March 2018 12:58 AM, Jan Kiszka wrote: >>> On 2018-03-14 05:54, Lokesh Vutla wrote: From: Lokesh Vutla Introduce cpu_id_last() api in order

Re: [PATCH 2/2] arm-common: gic-v3: Mark last CPUs GICR as last

On Thursday 15 March 2018 06:17 PM, Jan Kiszka wrote: > On 2018-03-15 00:17, Lokesh Vutla wrote: >> >> >> On Thursday 15 March 2018 01:02 AM, Jan Kiszka wrote: >>> On 2018-03-14 05:54, Lokesh Vutla wrote: From: Lokesh Vutla There are scenarios where Linux

Re: [PATCH 2/2] arm-common: gic-v3: Mark last CPUs GICR as last

On Thursday 15 March 2018 01:02 AM, Jan Kiszka wrote: > On 2018-03-14 05:54, Lokesh Vutla wrote: >> From: Lokesh Vutla >> >> There are scenarios where Linux boots up with less number of cores >> than the SoC supports. In such cases, finding GICR region marked with >>

Re: [PATCH 0/2] arm-commmon: gic-v3: Update detection of last GICR region

On Wednesday 14 March 2018 06:53 PM, Jan Kiszka wrote: > On 2018-03-14 05:54, Lokesh Vutla wrote: >> From: Lokesh Vutla >> >> This series introduces an api to find the last cpu available in the system >> CPU set. Using this, the GICR region corresponding to the last

Re: [PATCH 1/5] arm: remove superfluous include guards

On Wednesday 24 January 2018 07:12 PM, Ralf Ramsauer wrote: > We don't need include guards here. > > Signed-off-by: Ralf Ramsauer Sorry, may be it is obvious, but I did not understand why we don't need here. I also see we have guards in all other header files.

Re: [PATCH 2/5] tools: cell-linux: Make kernel decompression factor configurable

On Tuesday 09 January 2018 12:01 PM, Jan Kiszka wrote: > From: Jan Kiszka > > The required factor depends on the chosen compression method, and that > may vary. Have a large factor to account for aggressive compressions > (and increased memory needs during

Re: [PATCH 1/5] tools: cell-linux: Use minimal decompression space for ARM64

On Tuesday 09 January 2018 12:01 PM, Jan Kiszka wrote: > From: Jan Kiszka > > Factor out a default decompression factor for ARM because ARM64 does not > perform any compression so far, thus has a factor of 1 only. This allows > for more compact non-root Linux cell

Re: Loading kernel on Non-root cell in jetson-TX2.

On Saturday 06 January 2018 03:05 PM, a.ku...@matellio.com wrote: > Hi, > > > We are able to run jailhouse on Tx2 platform using 4.14-rc14-kernel, we are > able to enable root-cell and we can run non-root cell demo application which > is provided by jailhouse(gic-demo.bin). > > But we are

Re: cpu_down gets stuck, upon non-root cell creation

On Monday 11 December 2017 06:14 PM, Henning Schild wrote: > Am Mon, 11 Dec 2017 04:00:34 -0800 > schrieb : > >> Hi Henning, >> >>> I did not really look the the Linux-logs you provided. That is >>> because the Jailhouse side might be more interesting. I suspect >>> that

Re: [PATCH 5/8] arm-common: Migrate pending interrupts on shutdown

On Monday 09 October 2017 01:14 PM, Jan Kiszka wrote: > From: Jan Kiszka > > When we have interrupts pending for virtual injection, we need to > migrate them into the physical queue prior to disabling Jailhouse. > Failing to do so means loosing interrupts, most often

Re: ZCU102 environment questions

Hi Jan, On Tuesday 10 October 2017 07:10 PM, Jan Kiszka wrote: > On 2017-10-10 14:53, Constantin Petra wrote: >> OK, >> >> I understand, thanks for the config. So basically, looking (right) now at: >> http://git.kiszka.org/?p=linux.git;a=shortlog;h=refs/heads/queues/jailhouse >> >> All related

Re: Jailhouse compilation error?

Hi Arun, On Tuesday 26 September 2017 09:47 AM, Arun raj wrote: > Hi team, > > I'm trying to bring the jailhouse on jetson TX2 board.while compilation > itself i'm facing error.i'm having kernel 4.4.38 version.Is anyone > knkow > how to resolve this following error? > >

Re: [PATCH v4 15/17] inmates: arm-common: add support for issuing SGIs

On Tuesday 19 September 2017 10:25 PM, Ralf Ramsauer wrote: > I also implemented GICv3 support, but I'm lacking hardware to test it. > > Signed-off-by: Ralf Ramsauer > --- > Hi Nikhil, > > this uses now sysregs for accessing GICv3. Unfortunatelly I'm not able

Re: [PATCH v3 6/7] inmates, arm64: provide own sysregs.h

On Tuesday 19 September 2017 07:47 AM, 'Lokesh Vutla' via Jailhouse wrote: > > > On Monday 18 September 2017 03:37 PM, Ralf Ramsauer wrote: >> ARM inmates make use of hypervisor's sysregs accessors and helpers. In >> order to entirely decouple the hypervisor code fr

Re: [PATCH v2 0/3] arm: Add arch specific sysreg definitions

Hi Jan, On 9/14/2017 7:39 PM, Jan Kiszka wrote: > On 2017-09-14 16:03, Jan Kiszka wrote: >> On 2017-09-14 10:35, Lokesh Vutla wrote: >>> From: Lokesh Vutla >>> >>> arm: Add arch specific sysreg definitions >>> >>> Changes since v1: >>> - Fixed build error with ARM. >>> >>>

Re: [PATCH 2/3] arm: gicv3: Add arch specific List registers acccesses

On Thursday 14 September 2017 01:29 PM, Jan Kiszka wrote: > On 2017-09-12 14:05, Lokesh Vutla wrote: >> From: Lokesh Vutla >> >> With system register access enabled, gicv3 List registers >> can be accessed in the following manner: >> AArch64: ICH_LR_EL2 >> AArch32: ICH_LR,

Re: [PATCH 2/3] arm: gicv3: Add arch specific List registers acccesses

On Thursday 14 September 2017 01:29 PM, Jan Kiszka wrote: > On 2017-09-12 14:05, Lokesh Vutla wrote: >> From: Lokesh Vutla >> >> With system register access enabled, gicv3 List registers >> can be accessed in the following manner: >> AArch64: ICH_LR_EL2 >> AArch32: ICH_LR,

[RFC] Device-Tree for cell configuration

Hi All, When trying to add support for different combination of cell configurations, there was a feedback saying why not to use device-tree instead of .c files for cell configurations. I am sure this topic must have been discussed already. I am just curious about others opinion on using

[PATCH v7 2/5] arm-common: irqchip: Handle arch specific sgir access

gicv2: A write to GICD_SGIR should raise a SGI and hypervisor needs to be handled this as necessary gicv3: A write to GICD_SGIR needs to be ignored as affinity routing is enabled. Add support for handling these cases in each gic driver. Signed-off-by: Lokesh Vutla

[PATCH v7 5/5] arm-common: control: Explicitly specify routing mode for arm_cpu_kick()

Instead of relying on initial value, specify the routing mode of sgi for arm_cpu_kick(). Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm-common/control.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hypervisor/arch/arm-common/control.c

[PATCH v7 4/5] arm-common: irqchip: Make sure to handle interrupts after set pending

It has been the irqchip_set_pending() caller's responsibility to make sure to send a SGI_INJECT on target CPU. But it is not necessary that it is caller's responsibility. Instead send SGI_EVENT for a non-local injection from irqchip_set_pending(). Signed-off-by: Lokesh Vutla

[PATCH v7 0/5] arm-common: irqchip: Add affinity based routing

Changes since v6: - A bit more cleanups to get cpu target and cluster id from gic driver. - Do sgi_event at the end of irq_set_pending. Lokesh Vutla (5): arm-common: irqchip: Add support for deriving arch specific cpu target arm-common: irqchip: Handle arch specific sgir access arm-common:

Re: [PATCH v6 1/4] arm-common: irqchip: Fix handling of sgi routing mode 1

On Friday 08 September 2017 06:59 PM, Jan Kiszka wrote: > On 2017-09-08 13:12, Lokesh Vutla wrote: >> >> >> On Thursday 07 September 2017 07:32 PM, Jan Kiszka wrote: >>> On 2017-09-07 15:42, Jan Kiszka wrote: On 2017-09-07 11:39, Lokesh Vutla wrote: > When sgi is raised with routing

Re: [PATCH v6 4/4] arm-common: gic: Add arch specific arm_cpu_kick

On Thursday 07 September 2017 07:16 PM, Jan Kiszka wrote: > On 2017-09-07 11:39, Lokesh Vutla wrote: >> Targets field in sgi is different for gicv2 and gicv3. But >> arm_cpu_kick() populates cpu_id in the targets field independent >> of arch. Fixing it by creating gicv2 and givc3 specific >>

Re: [PATCH v6 1/4] arm-common: irqchip: Fix handling of sgi routing mode 1

On Thursday 07 September 2017 07:32 PM, Jan Kiszka wrote: > On 2017-09-07 15:42, Jan Kiszka wrote: >> On 2017-09-07 11:39, Lokesh Vutla wrote: >>> When sgi is raised with routing mode = 1, then hypervisor >>> should trap it and send sgi event to individual cpu within >>> the cell except the

[PATCH v6 0/4] arm-common: gic: Add affinity based routing

This series fixes couple of bugs with sgi handling of targets and adds support for affinity based routing. Changes since v5: - Fixed bugs with sgi routing mode 0 and 1 as reported by Jan - Add arch specific arm_cpu_kick(). Lokesh Vutla (4): arm-common: irqchip: Fix handling of sgi routing mode

[PATCH v6 3/4] arm-common: irqchip: Handle affinity based sgis for gic_handle_sgir_write()

Even though 'struct sgi' already supports for passing cluster_id, gic_handle_sgir_write() looks only for target fields and triggers sgis to its respective targets. This will fail in case of armv8 with affinity routing enabled. So parse all the affinity levels in sgi before sending sgi.

[PATCH v6 1/4] arm-common: irqchip: Fix handling of sgi routing mode 1

When sgi is raised with routing mode = 1, then hypervisor should trap it and send sgi event to individual cpu within the cell except the caller. Instead, jailhouse is doing a set_pending on each target cpu within the cell(except caller) and triggering sgi with routing mode = 1. This will

Re: [PATCH RFC/RFT 1/3] arm64: Add sysreg macro definitions

On Thursday 07 September 2017 03:07 PM, 'Lokesh Vutla' via Jailhouse wrote: > > > On Wednesday 06 September 2017 09:03 PM, Jan Kiszka wrote: >> On 2017-09-06 15:18, Lokesh Vutla wrote: >>> From: Nikhil Devshatwar <nikhil...@ti.com> >>> >>

[PATCH v6 4/4] arm-common: gic: Add arch specific arm_cpu_kick

Targets field in sgi is different for gicv2 and gicv3. But arm_cpu_kick() populates cpu_id in the targets field independent of arch. Fixing it by creating gicv2 and givc3 specific arm_cpu_kick() function and populate the fields accordingly. Signed-off-by: Lokesh Vutla ---

[PATCH v6 2/4] arm-common: irqchip: Fix handling of sgi routing mode 0

When a sgi is raised with routing mode 0, gic_handle_sgir_write() updates the target fields of the sgi with the target cpu_ids within the cell. But target fields are gic architecture dependent: gicv2: Expects the gicv2 cpu interface id to be written gicv3: Expects cpu_id Fixing it here.

Re: [PATCH RFC/RFT 1/3] arm64: Add sysreg macro definitions

On Wednesday 06 September 2017 09:03 PM, Jan Kiszka wrote: > On 2017-09-06 15:18, Lokesh Vutla wrote: >> From: Nikhil Devshatwar >> >> Add support for arm64 specific sysreg macro definitions. >> >> Signed-off-by: Nikhil Devshatwar >> Signed-off-by: Lokesh

Re: [PATCH v5 6/7] arm-common: control: Populate cluster_id and targets in sgi for arm_cpu_kick

On Wednesday 06 September 2017 07:42 PM, Jan Kiszka wrote: > On 2017-09-06 15:43, Jan Kiszka wrote: >> On 2017-09-06 14:14, Lokesh Vutla wrote: >>> >>> >>> On Wednesday 06 September 2017 05:27 PM, Jan Kiszka wrote: On 2017-09-06 08:14, Lokesh Vutla wrote: > Logical cpu_id may not match

Re: [PATCH v5 6/7] arm-common: control: Populate cluster_id and targets in sgi for arm_cpu_kick

On Wednesday 06 September 2017 07:13 PM, Jan Kiszka wrote: > On 2017-09-06 14:14, Lokesh Vutla wrote: >> >> >> On Wednesday 06 September 2017 05:27 PM, Jan Kiszka wrote: >>> On 2017-09-06 08:14, Lokesh Vutla wrote: Logical cpu_id may not match with aff0 always. So populate targets with

[PATCH RFC/RFT 0/3] arm64: Add arch specific sysreg definitions

As promised yesterday, here is an attempt to cleanup list registers and sysreg macro definitions. Lokesh Vutla (2): arm: gic: Add arch specific List registers acccesses arm: gic: Add arch specific sgi1r_el1 register definition Nikhil Devshatwar (1): arm64: Add sysreg macro definitions

Re: [PATCH v5 6/7] arm-common: control: Populate cluster_id and targets in sgi for arm_cpu_kick

On Wednesday 06 September 2017 05:27 PM, Jan Kiszka wrote: > On 2017-09-06 08:14, Lokesh Vutla wrote: >> Logical cpu_id may not match with aff0 always. So populate >> targets with aff0 and cluster_id from mpidr in sgi before >> sending sgi in arm_cpu_kick(). >> >> Signed-off-by: Lokesh Vutla

[PATCH v5 4/7] arm-common: Use cluster_id instead of affinity levels

For simplicity pass cluster id derived from mpidr instead of passing affinity levels separately. Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm-common/include/asm/irqchip.h | 7 ++- hypervisor/arch/arm-common/irqchip.c | 4 +---

[PATCH v5 3/7] arm: gicv3: Add support for affinity based irq routing

cpu_id(returned by first_cpu) may not match aff0 in mpidr. Fix this by always using affinity values in GICD_IROUTER. Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm/gic-v3.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git

[PATCH v5 7/7] arm-common: control: Explicitly specify routing mode for arm_cpu_kick()

Instead of relying on initial value, specify the routing mode of sgi for arm_cpu_kick(). Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm-common/control.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hypervisor/arch/arm-common/control.c

[PATCH v5 1/7] arm: gicv3: Fix the GICD_IROUTER offset

Commit 61e30277199e5 ("GICv3: Fix the GICD_IROUTER offset") in ATF[1] specifies that GICv3 documention mentions the wrong offset about GICD_IROUTER and gives proper calculation for interrupt id. Importing the same here. [1] https://github.com/ARM-software/arm-trusted-firmware Signed-off-by:

[PATCH v5 0/7] arm: gic: Add affinity based routing

This series is based on branch "next". It has couple of bug fixes and adds affinity based routing for arm gic. This should be able to go independently from gicv3 movement to common place. Changes since v4: - Updated couple of commit messages and macro definitions as suggested by Jan. - Removed

[PATCH v5 2/7] arm: gicv3: Fix detection of redistributor

MPIDR can be used to compare the GICR_TYPER register for redistributor base calculation. Logic is imported from kernel. Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm/gic-v3.c| 13 ++--- hypervisor/arch/arm/include/asm/sysregs.h | 7 +++

[PATCH v5 5/7] arm-common: irq-chip: Handle affinity based sgis for gic_handle_sgir_write()

Even though 'struct sgi' already supports for passing cluster_id, gic_handle_sgir_write() looks only for target fields and triggers sgis to its respective targets. This will fail in case of armv8 with affinity routing enabled. So parse all the affinity levels in sgi before sending sgi.

[PATCH v5 6/7] arm-common: control: Populate cluster_id and targets in sgi for arm_cpu_kick

Logical cpu_id may not match with aff0 always. So populate targets with aff0 and cluster_id from mpidr in sgi before sending sgi in arm_cpu_kick(). Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm-common/control.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

Re: [PATCH v4 0/7] arm: gic: Add affinity based routing

On 9/5/2017 9:08 PM, Jan Kiszka wrote: > On 2017-09-05 16:44, Lokesh Vutla wrote: >> >> >> On Tuesday 05 September 2017 08:02 PM, Lokesh Vutla wrote: >>> This series is based on branch "next". It has couple of bug >>> fixes and adds affinity based routing for arm gic. This should >>> be able to

Re: [PATCH v4 4/7] arm-common: Use cluster_id instead of affinity levels

On Tuesday 05 September 2017 09:02 PM, Jan Kiszka wrote: > On 2017-09-05 16:32, Lokesh Vutla wrote: >> For simplicity pass cluster id derived from mpidr instead of >> passing affinity levels separately. >> >> Signed-off-by: Lokesh Vutla >> --- >>

[PATCH v4 7/7] arm-common: control: Explicitly specify routing mode for arm_cpu_kick()

Instead of relying on initial value, specify the routing mode of sgi for arm_cpu_kick(). Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm-common/control.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hypervisor/arch/arm-common/control.c

[PATCH v4 1/7] arm: gicv3: Fix the GICD_IROUTER offset

Commit 61e30277199e5 ("GICv3: Fix the GICD_IROUTER offset") in ATF[1] specifies that GICv3 documention mentions the wrong offset about GICD_IROUTER and gives proper calculation for interrupt id. Importing the same here. [1] https://github.com/ARM-software/arm-trusted-firmware Signed-off-by:

[PATCH v4 4/7] arm-common: Use cluster_id instead of affinity levels

For simplicity pass cluster id derived from mpidr instead of passing affinity levels separately. Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm-common/include/asm/irqchip.h | 7 ++- hypervisor/arch/arm-common/irqchip.c | 4 +---

[PATCH v4 2/7] arm: gicv3: Fix detection of redistributor

MPIDR can be used to compare the GICR_TYPER register for redistributor base calculation. Logic is imported from kernel. Signed-off-by: Lokesh Vutla --- hypervisor/arch/arm/gic-v3.c| 13 ++--- hypervisor/arch/arm/include/asm/sysregs.h | 7 +++

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